ab_riscv_primitives/instructions/rv32/zk/zkn/
zknd.rs

1//! RV32 Zknd extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// 2-bit byte-select immediate for RV32 AES instructions.
13///
14/// Selects which byte of `rs2` is fed into the S-box: `bs ∈ {0,1,2,3}`.
15#[derive(Debug, Clone, Copy)]
16#[derive_const(PartialEq, Eq)]
17#[repr(u8)]
18pub enum Rv32AesBs {
19    B0 = 0,
20    B1 = 1,
21    B2 = 2,
22    B3 = 3,
23}
24
25impl From<Rv32AesBs> for u8 {
26    #[inline(always)]
27    fn from(bs: Rv32AesBs) -> Self {
28        bs as u8
29    }
30}
31
32impl From<Rv32AesBs> for usize {
33    #[inline(always)]
34    fn from(bs: Rv32AesBs) -> Self {
35        usize::from(bs as u8)
36    }
37}
38
39impl fmt::Display for Rv32AesBs {
40    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
41        fmt::Display::fmt(&(*self as u8), f)
42    }
43}
44
45impl Rv32AesBs {
46    /// Create from raw 2-bit value. Returns `None` if `bits > 3`.
47    #[inline(always)]
48    pub const fn from_bits(bits: u8) -> Option<Self> {
49        match bits {
50            0 => Some(Self::B0),
51            1 => Some(Self::B1),
52            2 => Some(Self::B2),
53            3 => Some(Self::B3),
54            _ => None,
55        }
56    }
57}
58
59/// RISC-V RV32 Zknd instructions (AES decryption)
60#[instruction]
61#[derive(Debug, Clone, Copy)]
62#[derive_const(PartialEq, Eq)]
63pub enum Rv32ZkndInstruction<Hart>
64where
65    Hart: HartConfig,
66{
67    /// AES final round decryption step: InvSubBytes on one byte of rs2,
68    /// rotated to the byte lane selected by bs, XOR'd into rs1.
69    ///
70    /// `rd = rs1 ^ rol32(INV_SBOX[(rs2 >> (bs*8)) & 0xff] as u32, bs*8)`
71    Aes32Dsi {
72        rd: Hart::Reg,
73        rs1: Hart::Reg,
74        rs2: Hart::Reg,
75        bs: Rv32AesBs,
76    },
77    /// AES middle round decryption step: InvSubBytes + partial InvMixColumns
78    /// on one byte of rs2, rotated to the byte lane selected by bs, XOR'd into rs1.
79    ///
80    /// `rd = rs1 ^ rol32(InvMixColByte(INV_SBOX[(rs2 >> (bs*8)) & 0xff]), bs*8)`
81    Aes32Dsmi {
82        rd: Hart::Reg,
83        rs1: Hart::Reg,
84        rs2: Hart::Reg,
85        bs: Rv32AesBs,
86    },
87}
88
89/// Encoding layout (R-type, opcode 0x33, funct3 0x0):
90///
91/// ```text
92/// [31:30] bs       - 2-bit byte select
93/// [29:25] funct5   - 0b1_0101 (aes32dsi) / 0b1_0111 (aes32dsmi)
94/// [24:20] rs2
95/// [19:15] rs1
96/// [14:12] funct3   - 0b000
97/// [11:7]  rd
98/// [6:0]   opcode   - 0b011_0011 (OP)
99/// ```
100///
101/// Ratified match/mask values (from riscv-opcodes):
102///   MATCH_AES32DSI  = 0x2a00_0033, MASK_AES32DSI  = 0x3e00_707f
103///   MATCH_AES32DSMI = 0x2e00_0033, MASK_AES32DSMI = 0x3e00_707f
104///
105/// `rd` and `rs1` are independent fields. The assembler convention places
106/// the accumulator in both rd and rs1 (the `rt` pattern), but the hardware
107/// does not require rd == rs1 and the decoder must not enforce it.
108#[instruction]
109const impl<Reg, Hart> Instruction for Rv32ZkndInstruction<Hart>
110where
111    Reg: [const] Register<Type = u32>,
112    Hart: [const] HartConfig<Reg = Reg>,
113{
114    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zknd", 1, 0)];
115
116    const ALIGNMENT: u8 = align_of::<u32>() as u8;
117
118    type Hart = Hart;
119
120    #[inline(always)]
121    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
122    fn try_decode(instruction: u32) -> Option<Self> {
123        let opcode = (instruction & 0b111_1111) as u8;
124        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
125        let funct3 = ((instruction >> 12) & 0b111) as u8;
126        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
127        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
128        let funct5 = ((instruction >> 25) & 0b1_1111) as u8;
129        let bs_bits = ((instruction >> 30) & 0b11) as u8;
130
131        // R-type OP opcode only
132        if opcode != 0b011_0011 {
133            None?;
134        }
135        if funct3 != 0b000 {
136            None?;
137        }
138
139        let rd = Reg::from_bits(rd_bits)?;
140        let rs1 = Reg::from_bits(rs1_bits)?;
141        let rs2 = Reg::from_bits(rs2_bits)?;
142        let bs = Rv32AesBs::from_bits(bs_bits)?;
143
144        match funct5 {
145            // aes32dsi:  bs[31:30] | 0b1_0101[29:25]
146            0b1_0101 => Some(Self::Aes32Dsi { rd, rs1, rs2, bs }),
147            // aes32dsmi: bs[31:30] | 0b1_0111[29:25]
148            0b1_0111 => Some(Self::Aes32Dsmi { rd, rs1, rs2, bs }),
149            _ => None,
150        }
151    }
152
153    #[inline(always)]
154    fn size(&self) -> u8 {
155        size_of::<u32>() as u8
156    }
157}
158
159#[instruction]
160impl<Reg, Hart> fmt::Display for Rv32ZkndInstruction<Hart>
161where
162    Reg: fmt::Display,
163    Hart: HartConfig<Reg = Reg>,
164{
165    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
166        match self {
167            Self::Aes32Dsi { rd, rs1, rs2, bs } => {
168                write!(f, "aes32dsi {rd}, {rs1}, {rs2}, {bs}")
169            }
170            Self::Aes32Dsmi { rd, rs1, rs2, bs } => {
171                write!(f, "aes32dsmi {rd}, {rs1}, {rs2}, {bs}")
172            }
173        }
174    }
175}
ab_riscv_primitives/instructions/rv32/zk/zkn/zknd.rs

ab_riscv_primitives/instructions/rv32/zk/zkn/
zknd.rs
