ab_riscv_primitives/instructions/rv32/zk/
zkn.rs

1//! RV32 Zkn extension
2
3pub mod zknd;
4pub mod zkne;
5pub mod zknh;
6
7use crate::instructions::Instruction;
8use crate::instructions::rv32::b::zbb::Rv32ZbbInstruction;
9use crate::instructions::rv32::b::zbc::Rv32ZbcInstruction;
10use crate::instructions::rv32::zk::zbkb::Rv32ZbkbInstruction;
11use crate::instructions::rv32::zk::zbkc::Rv32ZbkcInstruction;
12use crate::instructions::rv32::zk::zbkx::Rv32ZbkxInstruction;
13use crate::instructions::rv32::zk::zkn::zknd::{Rv32AesBs, Rv32ZkndInstruction};
14use crate::instructions::rv32::zk::zkn::zkne::Rv32ZkneInstruction;
15use crate::instructions::rv32::zk::zkn::zknh::Rv32ZknhInstruction;
16use crate::registers::general_purpose::Register;
17use ab_riscv_macros::instruction;
18use core::fmt;
19
20/// RISC-V RV32 Zkn (Zbkb + Zbkc + Zbkx + Zknd + Zkne + Zknh) instruction
21#[instruction(
22    inherit = [
23        Rv32ZbkbInstruction,
24        Rv32ZbkcInstruction,
25        Rv32ZbkxInstruction,
26        Rv32ZkndInstruction,
27        Rv32ZkneInstruction,
28        Rv32ZknhInstruction,
29    ]
30)]
31#[derive(Debug, Clone, Copy)]
32#[derive_const(PartialEq, Eq)]
33pub enum Rv32ZknInstruction<Reg> {}
34
35#[instruction]
36const impl<Reg> Instruction for Rv32ZknInstruction<Reg>
37where
38    Reg: [const] Register<Type = u32>,
39{
40    const ALIGNMENT: u8 = align_of::<u32>() as u8;
41
42    type Reg = Reg;
43
44    #[inline(always)]
45    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
46    fn try_decode(instruction: u32) -> Option<Self> {
47        None
48    }
49
50    #[inline(always)]
51    fn size(&self) -> u8 {
52        size_of::<u32>() as u8
53    }
54}
55
56#[instruction]
57impl<Reg> fmt::Display for Rv32ZknInstruction<Reg>
58where
59    Reg: fmt::Display + Copy,
60{
61    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
62        match self {}
63    }
64}
ab_riscv_primitives/instructions/rv32/zk/zkn.rs

ab_riscv_primitives/instructions/rv32/zk/
zkn.rs
