ab_riscv_primitives/instructions/rv32/zk/
zkn.rs

1//! RV32 Zkn extension
2
3pub mod zknd;
4pub mod zkne;
5pub mod zknh;
6
7use crate::instructions::Instruction;
8use crate::instructions::rv32::b::zbb::Rv32ZbbInstruction;
9use crate::instructions::rv32::b::zbc::Rv32ZbcInstruction;
10use crate::instructions::rv32::zk::zbkb::Rv32ZbkbInstruction;
11use crate::instructions::rv32::zk::zbkx::Rv32ZbkxInstruction;
12use crate::instructions::rv32::zk::zkn::zknd::{Rv32AesBs, Rv32ZkndInstruction};
13use crate::instructions::rv32::zk::zkn::zkne::Rv32ZkneInstruction;
14use crate::instructions::rv32::zk::zkn::zknh::Rv32ZknhInstruction;
15use crate::registers::general_purpose::Register;
16use ab_riscv_macros::instruction;
17use core::fmt;
18
19/// RISC-V RV32 Zkn (Zbkb + Zbkc + Zbkx + Zknd + Zkne + Zknh) instruction
20#[instruction(
21    inherit = [
22        Rv32ZbkbInstruction,
23        Rv32ZbkcInstruction,
24        Rv32ZbkxInstruction,
25        Rv32ZkndInstruction,
26        Rv32ZkneInstruction,
27        Rv32ZknhInstruction,
28    ]
29)]
30#[derive(Debug, Clone, Copy, PartialEq, Eq)]
31pub enum Rv32ZknInstruction<Reg> {}
32
33#[instruction]
34const impl<Reg> Instruction for Rv32ZknInstruction<Reg>
35where
36    Reg: [const] Register<Type = u32>,
37{
38    type Reg = Reg;
39
40    #[inline(always)]
41    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
42    fn try_decode(instruction: u32) -> Option<Self> {
43        None
44    }
45
46    #[inline(always)]
47    fn alignment() -> u8 {
48        align_of::<u32>() as u8
49    }
50
51    #[inline(always)]
52    fn size(&self) -> u8 {
53        size_of::<u32>() as u8
54    }
55}
56
57#[instruction]
58impl<Reg> fmt::Display for Rv32ZknInstruction<Reg>
59where
60    Reg: fmt::Display + Copy,
61{
62    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
63        match self {}
64    }
65}
ab_riscv_primitives/instructions/rv32/zk/zkn.rs

ab_riscv_primitives/instructions/rv32/zk/
zkn.rs
