ab_riscv_primitives/instructions/rv32/zk/
zbkb.rs

1//! RV32 Zbkb extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::rv32::b::zbb::Rv32ZbbZbkbSharedInstruction;
8use crate::instructions::utils::Shamt;
9use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
10use crate::registers::general_purpose::Register;
11use ab_riscv_macros::instruction;
12use core::fmt;
13
14/// RISC-V RV32 Zbkb instruction (Bit-manipulation for Cryptography)
15#[instruction(inherit = [Rv32ZbbZbkbSharedInstruction])]
16#[derive(Debug, Clone, Copy)]
17#[derive_const(PartialEq, Eq)]
18#[rustfmt::skip]
19pub enum Rv32ZbkbInstruction<Hart>
20where
21    Hart: HartConfig,
22{
23    /// Pack low 16 bits of `rs1` into `rd[15:0]`, low 16 bits of `rs2` into `rd[31:16]`
24    Pack { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
25    /// Pack low 8 bits of `rs1` into `rd[7:0]`, low 8 bits of `rs2` into `rd[15:8]`
26    Packh { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
27    /// Reverse bits in each byte of `rs1`
28    Brev8 { rd: Hart::Reg, rs1: Hart::Reg },
29    /// Bit-interleave: scatter lower-half bits of `rs1` to even positions, upper-half bits to odd
30    /// positions
31    Zip { rd: Hart::Reg, rs1: Hart::Reg },
32    /// Inverse of zip: gather even-position bits of `rs1` to lower half, odd-position bits to upper
33    /// half
34    Unzip { rd: Hart::Reg, rs1: Hart::Reg },
35}
36
37#[instruction]
38const impl<Reg, Hart> Instruction for Rv32ZbkbInstruction<Hart>
39where
40    Reg: [const] Register<Type = u32>,
41    Hart: [const] HartConfig<Reg = Reg>,
42{
43    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zbkb", 1, 0)];
44
45    const ALIGNMENT: u8 = align_of::<u32>() as u8;
46
47    type Hart = Hart;
48
49    #[inline(always)]
50    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
51    fn try_decode(instruction: u32) -> Option<Self> {
52        let opcode = (instruction & 0b111_1111) as u8;
53        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
54        let funct3 = ((instruction >> 12) & 0b111) as u8;
55        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
56        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
57        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
58        let funct12 = ((instruction >> 20) & 0xfff) as u16;
59
60        match opcode {
61            // OP-IMM (I-type): brev8, zip, unzip
62            0b001_0011 => {
63                let rd = Reg::from_bits(rd_bits)?;
64                let rs1 = Reg::from_bits(rs1_bits)?;
65                match funct3 {
66                    // brev8: funct12 = 0b011010000111 = 0x687
67                    0b101 if funct12 == 0b0110_1000_0111 => Some(Self::Brev8 { rd, rs1 }),
68                    // zip:   funct7=0000100, rs2=01111, funct3=001 -> funct12=0x08F
69                    0b001 if funct12 == 0b0000_1000_1111 => Some(Self::Zip { rd, rs1 }),
70                    // unzip: funct7=0000100, rs2=01111, funct3=101 -> funct12=0x08F
71                    0b101 if funct12 == 0b0000_1000_1111 => Some(Self::Unzip { rd, rs1 }),
72                    _ => None,
73                }
74            }
75            // OP (R-type): pack, packh
76            0b011_0011 => {
77                let rd = Reg::from_bits(rd_bits)?;
78                let rs1 = Reg::from_bits(rs1_bits)?;
79                let rs2 = Reg::from_bits(rs2_bits)?;
80                match (funct3, funct7) {
81                    // pack: funct3=100, funct7=0000100
82                    (0b100, 0b000_0100) => {
83                        // NOTE: `pack rd, rs1, x0` has exactly the same encoding and semantics
84                        // as Zbb's `zext.h`, which is cheaper to execute, so it is decoded as
85                        // `zext.h` when it is present in the instruction set, regardless of the
86                        // order in which extensions are inherited. The macro replaces `Self::Zexth`
87                        // with `None?` in instruction sets without it, which makes this a regular
88                        // `pack`.
89                        let zexth = if rs2_bits == 0 {
90                            try { Self::Zexth { rd, rs1 } }
91                        } else {
92                            None
93                        };
94                        if zexth.is_some() {
95                            zexth
96                        } else {
97                            Some(Self::Pack { rd, rs1, rs2 })
98                        }
99                    }
100                    // packh: funct3=111, funct7=0000100
101                    (0b111, 0b000_0100) => Some(Self::Packh { rd, rs1, rs2 }),
102                    _ => None,
103                }
104            }
105            _ => None,
106        }
107    }
108
109    #[inline(always)]
110    fn size(&self) -> u8 {
111        size_of::<u32>() as u8
112    }
113}
114
115#[instruction]
116impl<Reg, Hart> fmt::Display for Rv32ZbkbInstruction<Hart>
117where
118    Reg: fmt::Display + Copy,
119    Hart: HartConfig<Reg = Reg>,
120{
121    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
122        match self {
123            Self::Pack { rd, rs1, rs2 } => write!(f, "pack {rd}, {rs1}, {rs2}"),
124            Self::Packh { rd, rs1, rs2 } => write!(f, "packh {rd}, {rs1}, {rs2}"),
125            Self::Brev8 { rd, rs1 } => write!(f, "brev8 {rd}, {rs1}"),
126            Self::Zip { rd, rs1 } => write!(f, "zip {rd}, {rs1}"),
127            Self::Unzip { rd, rs1 } => write!(f, "unzip {rd}, {rs1}"),
128        }
129    }
130}
ab_riscv_primitives/instructions/rv32/zk/zbkb.rs

ab_riscv_primitives/instructions/rv32/zk/
zbkb.rs
