ab_riscv_primitives/instructions/rv32/zce/

zcb.rs

//! RV32 Zcb extension

#[cfg(test)]
mod tests;

use crate::hart::HartConfig;
use crate::instructions::rv32::c::zca::Rv32ZcaInstruction;
use crate::instructions::utils::{I24, Shamt};
use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
use crate::registers::general_purpose::Register;
use ab_riscv_macros::instruction;
use core::fmt;

/// RISC-V RV32 Zcb compressed instruction set.
///
/// All register operands are prime-field (x8–x15) registers.
#[instruction(
    inherit = [Rv32ZcaInstruction, Rv32ZcbOnlyInstruction],
)]
#[derive(Debug, Clone, Copy)]
#[derive_const(PartialEq, Eq)]
pub enum Rv32ZcbInstruction<Hart>
where
    Hart: HartConfig, {}

#[instruction]
const impl<Reg, Hart> Instruction for Rv32ZcbInstruction<Hart>
where
    Reg: [const] Register<Type = u32>,
    Hart: [const] HartConfig<Reg = Reg>,
{
    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zcb", 1, 0)];

    const ALIGNMENT: u8 = align_of::<u16>() as u8;

    type Hart = Hart;

    #[inline(always)]
    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
    fn try_decode(instruction: u32) -> Option<Self> {
        None
    }

    #[inline(always)]
    fn size(&self) -> u8 {
        size_of::<u16>() as u8
    }
}

#[instruction]
impl<Reg, Hart> fmt::Display for Rv32ZcbInstruction<Hart>
where
    Reg: fmt::Display + Copy,
    Hart: HartConfig<Reg = Reg>,
{
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {}
    }
}

/// Instruction that contains isolated Zcb instructions without inheriting Zca for testing purposes
#[instruction]
#[derive(Debug, Clone, Copy)]
#[derive_const(PartialEq, Eq)]
#[rustfmt::skip]
#[doc(hidden)]
pub enum Rv32ZcbOnlyInstruction<Hart>
where
    Hart: HartConfig,
{
    // Q00 loads / stores
    /// C.LBU  rd' = zero_extend(mem8\[rs1' + uimm])  uimm ∈ {0,1,2,3}
    CLbu { rd: Hart::Reg, rs1: Hart::Reg, uimm: u8 },
    /// C.LH   rd' = sign_extend(mem16\[rs1' + uimm])  uimm ∈ {0,2}
    CLh { rd: Hart::Reg, rs1: Hart::Reg, uimm: u8 },
    /// C.LHU  rd' = zero_extend(mem16\[rs1' + uimm])  uimm ∈ {0,2}
    CLhu { rd: Hart::Reg, rs1: Hart::Reg, uimm: u8 },
    /// C.SB   mem8\[rs1' + uimm] = rs2'  uimm ∈ {0,1,2,3}
    CSb { rs1: Hart::Reg, rs2: Hart::Reg, uimm: u8 },
    /// C.SH   mem16\[rs1' + uimm] = rs2'  uimm ∈ {0,2}
    CSh { rs1: Hart::Reg, rs2: Hart::Reg, uimm: u8 },

    // Q01 unary bit-manipulation
    /// C.ZEXT.B  rd' = rd' & 0xff
    CZextB { rd: Hart::Reg },
    /// C.SEXT.B  rd' = sext(rd'\[7:0])  (requires Zbb)
    #[instruction(if = [Rv32ZbbInstruction])]
    CSextB { rd: Hart::Reg },
    /// C.ZEXT.H  rd' = rd' & 0xffff  (requires Zbb)
    #[instruction(if = [Rv32ZbbInstruction])]
    CZextH { rd: Hart::Reg },
    /// C.SEXT.H  rd' = sext(rd'\[15:0])  (requires Zbb)
    #[instruction(if = [Rv32ZbbInstruction])]
    CSextH { rd: Hart::Reg },
    /// C.NOT  rd' = ~rd'
    CNot { rd: Hart::Reg },

    // Q01 binary
    /// C.MUL  rd' = (rd' * rs2')\[31:0]  (requires Zmmul, which M inherits)
    #[instruction(if = [Rv32ZmmulInstruction])]
    CMul { rd: Hart::Reg, rs2: Hart::Reg },
}

#[instruction]
const impl<Reg, Hart> Instruction for Rv32ZcbOnlyInstruction<Hart>
where
    Reg: [const] Register<Type = u32>,
    Hart: [const] HartConfig<Reg = Reg>,
{
    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[];

    const ALIGNMENT: u8 = align_of::<u16>() as u8;

    type Hart = Hart;

    #[inline(always)]
    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
    fn try_decode(instruction: u32) -> Option<Self> {
        /// Map a 3-bit "prime" register field to an absolute register number
        #[inline(always)]
        const fn prime_reg_bits(bits: u8) -> u8 {
            bits + 8
        }

        let inst = instruction as u16;
        let quadrant = inst & 0b11;
        let funct3 = ((inst >> 13) & 0b111) as u8;

        match quadrant {
            // Q00 funct3=100: C.LBU / C.LHU / C.LH / C.SB / C.SH
            0b00 if funct3 == 0b100 => {
                let sub = ((inst >> 10) & 0b111) as u8;
                let rs1_bits = prime_reg_bits(((inst >> 7) & 0b111) as u8);
                let rd_rs2_bits = prime_reg_bits(((inst >> 2) & 0b111) as u8);

                match sub {
                    // C.LBU  uimm[1]=inst[5], uimm[0]=inst[6]
                    0b000 => {
                        let uimm = ((((inst >> 5) & 1) << 1) | ((inst >> 6) & 1)) as u8;
                        let rs1 = Reg::from_bits(rs1_bits)?;
                        let rd = Reg::from_bits(rd_rs2_bits)?;
                        Some(Self::CLbu { rd, rs1, uimm })
                    }
                    // C.LHU (funct1=inst[6]=0) / C.LH (funct1=inst[6]=1)
                    // uimm[1]=inst[5], uimm[0]=0 (halfword aligned)
                    0b001 => {
                        let funct1 = ((inst >> 6) & 1) as u8;
                        let uimm = (((inst >> 5) & 1) as u8) << 1;
                        let rs1 = Reg::from_bits(rs1_bits)?;
                        let rd = Reg::from_bits(rd_rs2_bits)?;
                        if funct1 == 0 {
                            Some(Self::CLhu { rd, rs1, uimm })
                        } else {
                            Some(Self::CLh { rd, rs1, uimm })
                        }
                    }
                    // C.SB  uimm[1]=inst[5], uimm[0]=inst[6]
                    0b010 => {
                        let uimm = ((((inst >> 5) & 1) << 1) | ((inst >> 6) & 1)) as u8;
                        let rs1 = Reg::from_bits(rs1_bits)?;
                        let rs2 = Reg::from_bits(rd_rs2_bits)?;
                        Some(Self::CSb { rs1, rs2, uimm })
                    }
                    // C.SH  funct1=inst[6]=0, uimm[1]=inst[5]
                    0b011 => {
                        if ((inst >> 6) & 1) != 0 {
                            None?;
                        }
                        let uimm = (((inst >> 5) & 1) as u8) << 1;
                        let rs1 = Reg::from_bits(rs1_bits)?;
                        let rs2 = Reg::from_bits(rd_rs2_bits)?;
                        Some(Self::CSh { rs1, rs2, uimm })
                    }
                    _ => None,
                }
            }

            // Q01 funct3=100, funct2[11:10]=11, bit12=1: unary ops and C.MUL
            //
            // Encoding layout (per ratified Zcb spec):
            //   funct2b = inst[6:5]
            //   0b11 => unary ops, sub-op = inst[4:2]
            //   0b10 => C.MUL, rs2' = inst[4:2]
            //   0b00, 0b01 => reserved
            0b01 if funct3 == 0b100 => {
                let funct2_11_10 = ((inst >> 10) & 0b11) as u8;
                let bit12 = (inst >> 12) & 1;

                if funct2_11_10 != 0b11 || bit12 == 0 {
                    None?;
                }

                let rd_rs1_bits = prime_reg_bits(((inst >> 7) & 0b111) as u8);
                let funct2b = ((inst >> 5) & 0b11) as u8;
                let rs2_sub = ((inst >> 2) & 0b111) as u8;

                match funct2b {
                    // Unary ops: funct2b=0b11, sub-op in inst[4:2]
                    0b11 => {
                        let rd = Reg::from_bits(rd_rs1_bits)?;
                        match rs2_sub {
                            0b000 => Some(Self::CZextB { rd }),
                            0b001 => Some(Self::CSextB { rd }),
                            0b010 => Some(Self::CZextH { rd }),
                            0b011 => Some(Self::CSextH { rd }),
                            0b101 => Some(Self::CNot { rd }),
                            // 0b100, 0b110, 0b111 reserved
                            _ => None,
                        }
                    }
                    // C.MUL: funct2b=0b10, rs2' = inst[4:2]
                    0b10 => {
                        let rd = Reg::from_bits(rd_rs1_bits)?;
                        let rs2 = Reg::from_bits(prime_reg_bits(rs2_sub))?;
                        Some(Self::CMul { rd, rs2 })
                    }
                    // funct2b=0b00 and funct2b=0b01 are reserved in Zcb
                    _ => None,
                }
            }
            _ => None,
        }
    }

    #[inline(always)]
    fn size(&self) -> u8 {
        size_of::<u16>() as u8
    }
}

#[instruction]
impl<Reg, Hart> fmt::Display for Rv32ZcbOnlyInstruction<Hart>
where
    Reg: fmt::Display + Copy,
    Hart: HartConfig<Reg = Reg>,
{
    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
        match self {
            Self::CLbu { rd, rs1, uimm } => write!(f, "c.lbu {rd}, {uimm}({rs1})"),
            Self::CLh { rd, rs1, uimm } => write!(f, "c.lh {rd}, {uimm}({rs1})"),
            Self::CLhu { rd, rs1, uimm } => write!(f, "c.lhu {rd}, {uimm}({rs1})"),
            Self::CSb { rs1, rs2, uimm } => write!(f, "c.sb {rs2}, {uimm}({rs1})"),
            Self::CSh { rs1, rs2, uimm } => write!(f, "c.sh {rs2}, {uimm}({rs1})"),
            Self::CZextB { rd } => write!(f, "c.zext.b {rd}"),
            Self::CSextB { rd } => write!(f, "c.sext.b {rd}"),
            Self::CZextH { rd } => write!(f, "c.zext.h {rd}"),
            Self::CSextH { rd } => write!(f, "c.sext.h {rd}"),
            Self::CNot { rd } => write!(f, "c.not {rd}"),
            Self::CMul { rd, rs2 } => write!(f, "c.mul {rd}, {rs2}"),
        }
    }
}