ab_riscv_primitives/instructions/rv32/
zalasr.rs

1//! RV32 Zalasr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zalasr instruction (Load-Acquire/Store-Release).
12///
13/// Load-acquire instructions always carry an acquire annotation (not stored as a field since it
14/// is always `true`), plus an optional release annotation stored in `rl`. Store-release
15/// instructions always carry a release annotation (not stored as a field since it is always
16/// `true`), plus an optional acquire annotation stored in `aq`.
17#[instruction]
18#[derive(Debug, Clone, Copy)]
19#[derive_const(PartialEq, Eq)]
20pub enum Rv32ZalasrInstruction<Reg> {
21    /// Load-acquire byte
22    LbAq { rd: Reg, rs1: Reg, rl: bool },
23    /// Load-acquire halfword
24    LhAq { rd: Reg, rs1: Reg, rl: bool },
25    /// Load-acquire word
26    LwAq { rd: Reg, rs1: Reg, rl: bool },
27    /// Store-release byte
28    SbRl { rs1: Reg, rs2: Reg, aq: bool },
29    /// Store-release halfword
30    ShRl { rs1: Reg, rs2: Reg, aq: bool },
31    /// Store-release word
32    SwRl { rs1: Reg, rs2: Reg, aq: bool },
33}
34
35#[instruction]
36const impl<Reg> Instruction for Rv32ZalasrInstruction<Reg>
37where
38    Reg: [const] Register<Type = u32>,
39{
40    type Reg = Reg;
41
42    #[inline(always)]
43    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
44    fn try_decode(instruction: u32) -> Option<Self> {
45        let opcode = (instruction & 0b111_1111) as u8;
46        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
47        let funct3 = ((instruction >> 12) & 0b111) as u8;
48        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
49        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
50        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
51        let funct5 = funct7 >> 2;
52        let aq = (funct7 & 0b10) != 0;
53        let rl = (funct7 & 0b01) != 0;
54
55        match (opcode, funct5) {
56            // Load-acquire, `aq` bit is mandatory and `rs2` must be zero
57            (0b010_1111, 0b00110) => match (funct3, rs2_bits, aq) {
58                (0b000, 0, true) => {
59                    let rd = Reg::from_bits(rd_bits)?;
60                    let rs1 = Reg::from_bits(rs1_bits)?;
61                    Some(Self::LbAq { rd, rs1, rl })
62                }
63                (0b001, 0, true) => {
64                    let rd = Reg::from_bits(rd_bits)?;
65                    let rs1 = Reg::from_bits(rs1_bits)?;
66                    Some(Self::LhAq { rd, rs1, rl })
67                }
68                (0b010, 0, true) => {
69                    let rd = Reg::from_bits(rd_bits)?;
70                    let rs1 = Reg::from_bits(rs1_bits)?;
71                    Some(Self::LwAq { rd, rs1, rl })
72                }
73                _ => None,
74            },
75            // Store-release, `rl` bit is mandatory and `rd` must be zero
76            (0b010_1111, 0b00111) => match (funct3, rd_bits, rl) {
77                (0b000, 0, true) => {
78                    let rs1 = Reg::from_bits(rs1_bits)?;
79                    let rs2 = Reg::from_bits(rs2_bits)?;
80                    Some(Self::SbRl { rs1, rs2, aq })
81                }
82                (0b001, 0, true) => {
83                    let rs1 = Reg::from_bits(rs1_bits)?;
84                    let rs2 = Reg::from_bits(rs2_bits)?;
85                    Some(Self::ShRl { rs1, rs2, aq })
86                }
87                (0b010, 0, true) => {
88                    let rs1 = Reg::from_bits(rs1_bits)?;
89                    let rs2 = Reg::from_bits(rs2_bits)?;
90                    Some(Self::SwRl { rs1, rs2, aq })
91                }
92                _ => None,
93            },
94            _ => None,
95        }
96    }
97
98    #[inline(always)]
99    fn alignment() -> u8 {
100        align_of::<u32>() as u8
101    }
102
103    #[inline(always)]
104    fn size(&self) -> u8 {
105        size_of::<u32>() as u8
106    }
107}
108
109/// Format optional `rl` suffix for load-acquire display
110#[inline(always)]
111fn rl_suffix(rl: &bool) -> &'static str {
112    if *rl { ".aqrl" } else { ".aq" }
113}
114
115/// Format optional `aq` suffix for store-release display
116#[inline(always)]
117fn aq_suffix(aq: &bool) -> &'static str {
118    if *aq { ".aqrl" } else { ".rl" }
119}
120
121#[instruction]
122impl<Reg> fmt::Display for Rv32ZalasrInstruction<Reg>
123where
124    Reg: fmt::Display,
125{
126    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
127        match self {
128            Self::LbAq { rd, rs1, rl } => write!(f, "lb{} {rd}, ({rs1})", rl_suffix(rl)),
129            Self::LhAq { rd, rs1, rl } => write!(f, "lh{} {rd}, ({rs1})", rl_suffix(rl)),
130            Self::LwAq { rd, rs1, rl } => write!(f, "lw{} {rd}, ({rs1})", rl_suffix(rl)),
131            Self::SbRl { rs1, rs2, aq } => write!(f, "sb{} {rs2}, ({rs1})", aq_suffix(aq)),
132            Self::ShRl { rs1, rs2, aq } => write!(f, "sh{} {rs2}, ({rs1})", aq_suffix(aq)),
133            Self::SwRl { rs1, rs2, aq } => write!(f, "sw{} {rs2}, ({rs1})", aq_suffix(aq)),
134        }
135    }
136}
ab_riscv_primitives/instructions/rv32/zalasr.rs

ab_riscv_primitives/instructions/rv32/
zalasr.rs
