ab_riscv_primitives/instructions/rv32/
zalasr.rs

1//! RV32 Zalasr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zalasr instruction (Load-Acquire/Store-Release).
13///
14/// Load-acquire instructions always carry an acquire annotation (not stored as a field since it
15/// is always `true`), plus an optional release annotation stored in `rl`. Store-release
16/// instructions always carry a release annotation (not stored as a field since it is always
17/// `true`), plus an optional acquire annotation stored in `aq`.
18#[instruction]
19#[derive(Debug, Clone, Copy)]
20#[derive_const(PartialEq, Eq)]
21#[rustfmt::skip]
22pub enum Rv32ZalasrInstruction<Hart>
23where
24    Hart: HartConfig,
25{
26    /// Load-acquire byte
27    LbAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
28    /// Load-acquire halfword
29    LhAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
30    /// Load-acquire word
31    LwAq { rd: Hart::Reg, rs1: Hart::Reg, rl: bool },
32    /// Store-release byte
33    SbRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
34    /// Store-release halfword
35    ShRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
36    /// Store-release word
37    SwRl { rs1: Hart::Reg, rs2: Hart::Reg, aq: bool },
38}
39
40#[instruction]
41const impl<Reg, Hart> Instruction for Rv32ZalasrInstruction<Hart>
42where
43    Reg: [const] Register<Type = u32>,
44    Hart: [const] HartConfig<Reg = Reg>,
45{
46    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zalasr", 1, 0)];
47
48    const ALIGNMENT: u8 = align_of::<u32>() as u8;
49
50    type Hart = Hart;
51
52    #[inline(always)]
53    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
54    fn try_decode(instruction: u32) -> Option<Self> {
55        let opcode = (instruction & 0b111_1111) as u8;
56        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
57        let funct3 = ((instruction >> 12) & 0b111) as u8;
58        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
59        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
60        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
61        let funct5 = funct7 >> 2;
62        let aq = (funct7 & 0b10) != 0;
63        let rl = (funct7 & 0b01) != 0;
64
65        match (opcode, funct5) {
66            // Load-acquire, `aq` bit is mandatory and `rs2` must be zero
67            (0b010_1111, 0b00110) => match (funct3, rs2_bits, aq) {
68                (0b000, 0, true) => {
69                    let rd = Reg::from_bits(rd_bits)?;
70                    let rs1 = Reg::from_bits(rs1_bits)?;
71                    Some(Self::LbAq { rd, rs1, rl })
72                }
73                (0b001, 0, true) => {
74                    let rd = Reg::from_bits(rd_bits)?;
75                    let rs1 = Reg::from_bits(rs1_bits)?;
76                    Some(Self::LhAq { rd, rs1, rl })
77                }
78                (0b010, 0, true) => {
79                    let rd = Reg::from_bits(rd_bits)?;
80                    let rs1 = Reg::from_bits(rs1_bits)?;
81                    Some(Self::LwAq { rd, rs1, rl })
82                }
83                _ => None,
84            },
85            // Store-release, `rl` bit is mandatory and `rd` must be zero
86            (0b010_1111, 0b00111) => match (funct3, rd_bits, rl) {
87                (0b000, 0, true) => {
88                    let rs1 = Reg::from_bits(rs1_bits)?;
89                    let rs2 = Reg::from_bits(rs2_bits)?;
90                    Some(Self::SbRl { rs1, rs2, aq })
91                }
92                (0b001, 0, true) => {
93                    let rs1 = Reg::from_bits(rs1_bits)?;
94                    let rs2 = Reg::from_bits(rs2_bits)?;
95                    Some(Self::ShRl { rs1, rs2, aq })
96                }
97                (0b010, 0, true) => {
98                    let rs1 = Reg::from_bits(rs1_bits)?;
99                    let rs2 = Reg::from_bits(rs2_bits)?;
100                    Some(Self::SwRl { rs1, rs2, aq })
101                }
102                _ => None,
103            },
104            _ => None,
105        }
106    }
107
108    #[inline(always)]
109    fn size(&self) -> u8 {
110        size_of::<u32>() as u8
111    }
112}
113
114/// Format optional `rl` suffix for load-acquire display
115#[inline(always)]
116fn rl_suffix(rl: &bool) -> &'static str {
117    if *rl { ".aqrl" } else { ".aq" }
118}
119
120/// Format optional `aq` suffix for store-release display
121#[inline(always)]
122fn aq_suffix(aq: &bool) -> &'static str {
123    if *aq { ".aqrl" } else { ".rl" }
124}
125
126#[instruction]
127impl<Reg, Hart> fmt::Display for Rv32ZalasrInstruction<Hart>
128where
129    Reg: fmt::Display,
130    Hart: HartConfig<Reg = Reg>,
131{
132    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
133        match self {
134            Self::LbAq { rd, rs1, rl } => write!(f, "lb{} {rd}, ({rs1})", rl_suffix(rl)),
135            Self::LhAq { rd, rs1, rl } => write!(f, "lh{} {rd}, ({rs1})", rl_suffix(rl)),
136            Self::LwAq { rd, rs1, rl } => write!(f, "lw{} {rd}, ({rs1})", rl_suffix(rl)),
137            Self::SbRl { rs1, rs2, aq } => write!(f, "sb{} {rs2}, ({rs1})", aq_suffix(aq)),
138            Self::ShRl { rs1, rs2, aq } => write!(f, "sh{} {rs2}, ({rs1})", aq_suffix(aq)),
139            Self::SwRl { rs1, rs2, aq } => write!(f, "sw{} {rs2}, ({rs1})", aq_suffix(aq)),
140        }
141    }
142}
ab_riscv_primitives/instructions/rv32/zalasr.rs

ab_riscv_primitives/instructions/rv32/
zalasr.rs
