ab_riscv_primitives/instructions/rv32/
zacas.rs

1//! RV32 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv32::a::zaamo::Rv32ZaamoInstruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zacas instruction (Atomic Compare-and-Swap)
13#[instruction(inherit = [Rv32ZaamoInstruction])]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv32ZacasInstruction<Reg> {
18    /// Compare-and-swap word
19    AmocasW { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
20    /// Compare-and-swap doubleword, using register pairs `(rd, rd_hi)` and `(rs2, rs2_hi)` since
21    /// RV32 registers are only 32 bits wide
22    AmocasD { rd: Reg, rs1: Reg, rs2: Reg, rd_hi: Reg, rs2_hi: Reg, aq: bool, rl: bool },
23}
24
25#[instruction]
26const impl<Reg> Instruction for Rv32ZacasInstruction<Reg>
27where
28    Reg: [const] Register<Type = u32>,
29{
30    const ALIGNMENT: u8 = align_of::<u32>() as u8;
31
32    type Reg = Reg;
33
34    #[inline(always)]
35    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
36    fn try_decode(instruction: u32) -> Option<Self> {
37        let opcode = (instruction & 0b111_1111) as u8;
38        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
39        let funct3 = ((instruction >> 12) & 0b111) as u8;
40        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
41        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
42        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
43
44        match (opcode, funct3, funct7 >> 2) {
45            // AMOCAS.W
46            (0b010_1111, 0b010, 0b00101) => {
47                let rd = Reg::from_bits(rd_bits)?;
48                let rs1 = Reg::from_bits(rs1_bits)?;
49                let rs2 = Reg::from_bits(rs2_bits)?;
50                let aq = (funct7 & 0b10) != 0;
51                let rl = (funct7 & 0b01) != 0;
52
53                Some(Self::AmocasW {
54                    rd,
55                    rs1,
56                    rs2,
57                    aq,
58                    rl,
59                })
60            }
61            // AMOCAS.D, register-pair mode (RV32)
62            (0b010_1111, 0b011, 0b00101) => {
63                match (rd_bits & 1, rs2_bits & 1) {
64                    // Both halves of the register pairs must be even numbered, otherwise the
65                    // encoding is reserved
66                    (0, 0) => {
67                        let rs1 = Reg::from_bits(rs1_bits)?;
68                        let rd = Reg::from_bits(rd_bits)?;
69                        let rd_hi = Reg::from_bits(rd_bits + 1)?;
70                        let rs2 = Reg::from_bits(rs2_bits)?;
71                        let rs2_hi = Reg::from_bits(rs2_bits + 1)?;
72                        let aq = (funct7 & 0b10) != 0;
73                        let rl = (funct7 & 0b01) != 0;
74
75                        Some(Self::AmocasD {
76                            rd,
77                            rs1,
78                            rs2,
79                            rd_hi,
80                            rs2_hi,
81                            aq,
82                            rl,
83                        })
84                    }
85                    _ => None,
86                }
87            }
88            _ => None,
89        }
90    }
91
92    #[inline(always)]
93    fn size(&self) -> u8 {
94        size_of::<u32>() as u8
95    }
96}
97
98/// Format `aq`/`rl` suffix for display
99#[inline(always)]
100fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
101    match (*aq, *rl) {
102        (false, false) => "",
103        (true, false) => ".aq",
104        (false, true) => ".rl",
105        (true, true) => ".aqrl",
106    }
107}
108
109#[instruction]
110impl<Reg> fmt::Display for Rv32ZacasInstruction<Reg>
111where
112    Reg: fmt::Display + Copy,
113{
114    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
115        #[rustfmt::skip]
116        match self {
117            Self::AmocasW { rd, rs1, rs2, aq, rl } => {
118                write!(f, "amocas.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl))
119            }
120            Self::AmocasD { rd, rs1, rs2, rd_hi, rs2_hi, aq, rl } => {
121                write!(
122                    f,
123                    "amocas.d{} {rd}, {rd_hi}, {rs2}, {rs2_hi}, ({rs1})",
124                    aq_rl_suffix(aq, rl)
125                )
126            }
127        }
128    }
129}
ab_riscv_primitives/instructions/rv32/zacas.rs

ab_riscv_primitives/instructions/rv32/
zacas.rs
