ab_riscv_primitives/instructions/rv32/
zacas.rs

1//! RV32 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::rv32::a::zaamo::Rv32ZaamoInstruction;
8use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV32 Zacas instruction (Atomic Compare-and-Swap)
14#[instruction(inherit = [Rv32ZaamoInstruction])]
15#[derive(Debug, Clone, Copy)]
16#[derive_const(PartialEq, Eq)]
17#[rustfmt::skip]
18pub enum Rv32ZacasInstruction<Hart>
19where
20    Hart: HartConfig,
21{
22    /// Compare-and-swap word
23    AmocasW { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, aq: bool, rl: bool },
24    // TODO: Register pairs are not enforced by types. Decoding only produces even `rd` and `rs2`
25    //  with `rd_hi` and `rs2_hi` being the registers right after them, and execution relies on that
26    //  instead of checking it again, like with other invariants checked by the decoder, so manually
27    //  constructed instructions can use arbitrary registers (not a memory safety issue). A type for
28    //  register pairs isn't an option yet: every instruction stores `rs1` and `rs2` with the same
29    //  type at the same position, so that reading operands compiles to reads at fixed offsets.
30    //  Revisit once `rs1` and `rs2` are no longer added to every instruction unconditionally, which
31    //  requires https://github.com/rust-lang/rfcs/pull/4001.
32    /// Compare-and-swap doubleword, using register pairs `(rd, rd_hi)` and `(rs2, rs2_hi)` since
33    /// RV32 registers are only 32 bits wide
34    AmocasD { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, rd_hi: Hart::Reg, rs2_hi: Hart::Reg, aq: bool, rl: bool },
35}
36
37#[instruction]
38const impl<Reg, Hart> Instruction for Rv32ZacasInstruction<Hart>
39where
40    Reg: [const] Register<Type = u32>,
41    Hart: [const] HartConfig<Reg = Reg>,
42{
43    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zacas", 1, 0)];
44
45    const ALIGNMENT: u8 = align_of::<u32>() as u8;
46
47    type Hart = Hart;
48
49    #[inline(always)]
50    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
51    fn try_decode(instruction: u32) -> Option<Self> {
52        let opcode = (instruction & 0b111_1111) as u8;
53        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
54        let funct3 = ((instruction >> 12) & 0b111) as u8;
55        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
56        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
57        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
58
59        match (opcode, funct3, funct7 >> 2) {
60            // AMOCAS.W
61            (0b010_1111, 0b010, 0b00101) => {
62                let rd = Reg::from_bits(rd_bits)?;
63                let rs1 = Reg::from_bits(rs1_bits)?;
64                let rs2 = Reg::from_bits(rs2_bits)?;
65                let aq = (funct7 & 0b10) != 0;
66                let rl = (funct7 & 0b01) != 0;
67
68                Some(Self::AmocasW {
69                    rd,
70                    rs1,
71                    rs2,
72                    aq,
73                    rl,
74                })
75            }
76            // AMOCAS.D, register-pair mode (RV32)
77            (0b010_1111, 0b011, 0b00101) => {
78                match (rd_bits & 1, rs2_bits & 1) {
79                    // Both halves of the register pairs must be even numbered, otherwise the
80                    // encoding is reserved
81                    (0, 0) => {
82                        let rs1 = Reg::from_bits(rs1_bits)?;
83                        let rd = Reg::from_bits(rd_bits)?;
84                        let rd_hi = Reg::from_bits(rd_bits + 1)?;
85                        let rs2 = Reg::from_bits(rs2_bits)?;
86                        let rs2_hi = Reg::from_bits(rs2_bits + 1)?;
87                        let aq = (funct7 & 0b10) != 0;
88                        let rl = (funct7 & 0b01) != 0;
89
90                        Some(Self::AmocasD {
91                            rd,
92                            rs1,
93                            rs2,
94                            rd_hi,
95                            rs2_hi,
96                            aq,
97                            rl,
98                        })
99                    }
100                    _ => None,
101                }
102            }
103            _ => None,
104        }
105    }
106
107    #[inline(always)]
108    fn size(&self) -> u8 {
109        size_of::<u32>() as u8
110    }
111}
112
113/// Format `aq`/`rl` suffix for display
114#[inline(always)]
115fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
116    match (*aq, *rl) {
117        (false, false) => "",
118        (true, false) => ".aq",
119        (false, true) => ".rl",
120        (true, true) => ".aqrl",
121    }
122}
123
124#[instruction]
125impl<Reg, Hart> fmt::Display for Rv32ZacasInstruction<Hart>
126where
127    Reg: fmt::Display + Copy,
128    Hart: HartConfig<Reg = Reg>,
129{
130    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
131        #[rustfmt::skip]
132        match self {
133            Self::AmocasW { rd, rs1, rs2, aq, rl } => {
134                write!(f, "amocas.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl))
135            }
136            Self::AmocasD { rd, rs1, rs2, rd_hi, rs2_hi, aq, rl } => {
137                write!(
138                    f,
139                    "amocas.d{} {rd}, {rd_hi}, {rs2}, {rs2_hi}, ({rs1})",
140                    aq_rl_suffix(aq, rl)
141                )
142            }
143        }
144    }
145}
ab_riscv_primitives/instructions/rv32/zacas.rs

ab_riscv_primitives/instructions/rv32/
zacas.rs
