ab_riscv_primitives/instructions/rv32/
zacas.rs

1//! RV32 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::rv32::a::zaamo::Rv32ZaamoInstruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zacas instruction (Atomic Compare-and-Swap)
13#[instruction(inherit = [Rv32ZaamoInstruction])]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv32ZacasInstruction<Reg> {
18    /// Compare-and-swap word
19    AmocasW { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
20    /// Compare-and-swap doubleword, using register pairs `(rd, rd_hi)` and `(rs2, rs2_hi)` since
21    /// RV32 registers are only 32 bits wide
22    AmocasD { rd: Reg, rs1: Reg, rs2: Reg, rd_hi: Reg, rs2_hi: Reg, aq: bool, rl: bool },
23}
24
25#[instruction]
26const impl<Reg> Instruction for Rv32ZacasInstruction<Reg>
27where
28    Reg: [const] Register<Type = u32>,
29{
30    type Reg = Reg;
31
32    #[inline(always)]
33    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
34    fn try_decode(instruction: u32) -> Option<Self> {
35        let opcode = (instruction & 0b111_1111) as u8;
36        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
37        let funct3 = ((instruction >> 12) & 0b111) as u8;
38        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
39        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
40        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
41
42        match (opcode, funct3, funct7 >> 2) {
43            // AMOCAS.W
44            (0b010_1111, 0b010, 0b00101) => {
45                let rd = Reg::from_bits(rd_bits)?;
46                let rs1 = Reg::from_bits(rs1_bits)?;
47                let rs2 = Reg::from_bits(rs2_bits)?;
48                let aq = (funct7 & 0b10) != 0;
49                let rl = (funct7 & 0b01) != 0;
50
51                Some(Self::AmocasW {
52                    rd,
53                    rs1,
54                    rs2,
55                    aq,
56                    rl,
57                })
58            }
59            // AMOCAS.D, register-pair mode (RV32)
60            (0b010_1111, 0b011, 0b00101) => {
61                match (rd_bits & 1, rs2_bits & 1) {
62                    // Both halves of the register pairs must be even numbered, otherwise the
63                    // encoding is reserved
64                    (0, 0) => {
65                        let rs1 = Reg::from_bits(rs1_bits)?;
66                        let rd = Reg::from_bits(rd_bits)?;
67                        let rd_hi = Reg::from_bits(rd_bits + 1)?;
68                        let rs2 = Reg::from_bits(rs2_bits)?;
69                        let rs2_hi = Reg::from_bits(rs2_bits + 1)?;
70                        let aq = (funct7 & 0b10) != 0;
71                        let rl = (funct7 & 0b01) != 0;
72
73                        Some(Self::AmocasD {
74                            rd,
75                            rs1,
76                            rs2,
77                            rd_hi,
78                            rs2_hi,
79                            aq,
80                            rl,
81                        })
82                    }
83                    _ => None,
84                }
85            }
86            _ => None,
87        }
88    }
89
90    #[inline(always)]
91    fn alignment() -> u8 {
92        align_of::<u32>() as u8
93    }
94
95    #[inline(always)]
96    fn size(&self) -> u8 {
97        size_of::<u32>() as u8
98    }
99}
100
101/// Format `aq`/`rl` suffix for display
102#[inline(always)]
103fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
104    match (*aq, *rl) {
105        (false, false) => "",
106        (true, false) => ".aq",
107        (false, true) => ".rl",
108        (true, true) => ".aqrl",
109    }
110}
111
112#[instruction]
113impl<Reg> fmt::Display for Rv32ZacasInstruction<Reg>
114where
115    Reg: fmt::Display + Copy,
116{
117    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
118        #[rustfmt::skip]
119        match self {
120            Self::AmocasW { rd, rs1, rs2, aq, rl } => {
121                write!(f, "amocas.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl))
122            }
123            Self::AmocasD { rd, rs1, rs2, rd_hi, rs2_hi, aq, rl } => {
124                write!(
125                    f,
126                    "amocas.d{} {rd}, {rd_hi}, {rs2}, {rs2_hi}, ({rs1})",
127                    aq_rl_suffix(aq, rl)
128                )
129            }
130        }
131    }
132}
ab_riscv_primitives/instructions/rv32/zacas.rs

ab_riscv_primitives/instructions/rv32/
zacas.rs
