ab_riscv_primitives/instructions/rv32/m/
zmmul.rs

1//! RV32 Zmmul extension (multiplication subset of M extension)
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zmmul instruction
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv32ZmmulInstruction<Hart>
18where
19    Hart: HartConfig,
20{
21    Mul { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
22    Mulh { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
23    Mulhsu { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
24    Mulhu { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
25}
26
27#[instruction]
28const impl<Reg, Hart> Instruction for Rv32ZmmulInstruction<Hart>
29where
30    Reg: [const] Register<Type = u32>,
31    Hart: [const] HartConfig<Reg = Reg>,
32{
33    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zmmul", 1, 0)];
34
35    const ALIGNMENT: u8 = align_of::<u32>() as u8;
36
37    type Hart = Hart;
38
39    #[inline(always)]
40    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
41    fn try_decode(instruction: u32) -> Option<Self> {
42        let opcode = (instruction & 0b111_1111) as u8;
43        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
44        let funct3 = ((instruction >> 12) & 0b111) as u8;
45        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
46        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
47        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
48
49        match opcode {
50            // R-type
51            0b011_0011 => {
52                let rd = Reg::from_bits(rd_bits)?;
53                let rs1 = Reg::from_bits(rs1_bits)?;
54                let rs2 = Reg::from_bits(rs2_bits)?;
55                match (funct3, funct7) {
56                    (0b000, 0b000_0001) => Some(Self::Mul { rd, rs1, rs2 }),
57                    (0b001, 0b000_0001) => Some(Self::Mulh { rd, rs1, rs2 }),
58                    (0b010, 0b000_0001) => Some(Self::Mulhsu { rd, rs1, rs2 }),
59                    (0b011, 0b000_0001) => Some(Self::Mulhu { rd, rs1, rs2 }),
60                    _ => None,
61                }
62            }
63            _ => None,
64        }
65    }
66
67    #[inline(always)]
68    fn size(&self) -> u8 {
69        size_of::<u32>() as u8
70    }
71}
72
73#[instruction]
74impl<Reg, Hart> fmt::Display for Rv32ZmmulInstruction<Hart>
75where
76    Reg: fmt::Display,
77    Hart: HartConfig<Reg = Reg>,
78{
79    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
80        match self {
81            Self::Mul { rd, rs1, rs2 } => write!(f, "mul {rd}, {rs1}, {rs2}"),
82            Self::Mulh { rd, rs1, rs2 } => write!(f, "mulh {rd}, {rs1}, {rs2}"),
83            Self::Mulhsu { rd, rs1, rs2 } => write!(f, "mulhsu {rd}, {rs1}, {rs2}"),
84            Self::Mulhu { rd, rs1, rs2 } => write!(f, "mulhu {rd}, {rs1}, {rs2}"),
85        }
86    }
87}
ab_riscv_primitives/instructions/rv32/m/zmmul.rs

ab_riscv_primitives/instructions/rv32/m/
zmmul.rs
