ab_riscv_primitives/instructions/rv32/
m.rs

1//! RV32 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::instructions::Instruction;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 M instruction
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16pub enum Rv32MInstruction<Reg> {
17    Mul { rd: Reg, rs1: Reg, rs2: Reg },
18    Mulh { rd: Reg, rs1: Reg, rs2: Reg },
19    Mulhsu { rd: Reg, rs1: Reg, rs2: Reg },
20    Mulhu { rd: Reg, rs1: Reg, rs2: Reg },
21    Div { rd: Reg, rs1: Reg, rs2: Reg },
22    Divu { rd: Reg, rs1: Reg, rs2: Reg },
23    Rem { rd: Reg, rs1: Reg, rs2: Reg },
24    Remu { rd: Reg, rs1: Reg, rs2: Reg },
25}
26
27#[instruction]
28const impl<Reg> Instruction for Rv32MInstruction<Reg>
29where
30    Reg: [const] Register<Type = u32>,
31{
32    const ALIGNMENT: u8 = align_of::<u32>() as u8;
33
34    type Reg = Reg;
35
36    #[inline(always)]
37    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
38    fn try_decode(instruction: u32) -> Option<Self> {
39        let opcode = (instruction & 0b111_1111) as u8;
40        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
41        let funct3 = ((instruction >> 12) & 0b111) as u8;
42        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
43        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
44        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
45
46        match opcode {
47            // R-type
48            0b011_0011 => {
49                let rd = Reg::from_bits(rd_bits)?;
50                let rs1 = Reg::from_bits(rs1_bits)?;
51                let rs2 = Reg::from_bits(rs2_bits)?;
52                match (funct3, funct7) {
53                    (0b000, 0b000_0001) => Some(Self::Mul { rd, rs1, rs2 }),
54                    (0b001, 0b000_0001) => Some(Self::Mulh { rd, rs1, rs2 }),
55                    (0b010, 0b000_0001) => Some(Self::Mulhsu { rd, rs1, rs2 }),
56                    (0b011, 0b000_0001) => Some(Self::Mulhu { rd, rs1, rs2 }),
57                    (0b100, 0b000_0001) => Some(Self::Div { rd, rs1, rs2 }),
58                    (0b101, 0b000_0001) => Some(Self::Divu { rd, rs1, rs2 }),
59                    (0b110, 0b000_0001) => Some(Self::Rem { rd, rs1, rs2 }),
60                    (0b111, 0b000_0001) => Some(Self::Remu { rd, rs1, rs2 }),
61                    _ => None,
62                }
63            }
64            _ => None,
65        }
66    }
67
68    #[inline(always)]
69    fn size(&self) -> u8 {
70        size_of::<u32>() as u8
71    }
72}
73
74#[instruction]
75impl<Reg> fmt::Display for Rv32MInstruction<Reg>
76where
77    Reg: fmt::Display,
78{
79    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
80        match self {
81            Self::Mul { rd, rs1, rs2 } => write!(f, "mul {rd}, {rs1}, {rs2}"),
82            Self::Mulh { rd, rs1, rs2 } => write!(f, "mulh {rd}, {rs1}, {rs2}"),
83            Self::Mulhsu { rd, rs1, rs2 } => write!(f, "mulhsu {rd}, {rs1}, {rs2}"),
84            Self::Mulhu { rd, rs1, rs2 } => write!(f, "mulhu {rd}, {rs1}, {rs2}"),
85            Self::Div { rd, rs1, rs2 } => write!(f, "div {rd}, {rs1}, {rs2}"),
86            Self::Divu { rd, rs1, rs2 } => write!(f, "divu {rd}, {rs1}, {rs2}"),
87            Self::Rem { rd, rs1, rs2 } => write!(f, "rem {rd}, {rs1}, {rs2}"),
88            Self::Remu { rd, rs1, rs2 } => write!(f, "remu {rd}, {rs1}, {rs2}"),
89        }
90    }
91}
ab_riscv_primitives/instructions/rv32/m.rs

ab_riscv_primitives/instructions/rv32/
m.rs
