Skip to main content

ab_riscv_primitives/instructions/rv32/c/
zca.rs

1//! RV32 Zca extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::instructions::utils::I24;
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zca compressed instruction set
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv32ZcaInstruction<Reg> {
18    // Quadrant 00
19    /// C.ADDI4SPN  rd' = sp + nzuimm  (nzuimm != 0)
20    CAddi4spn { rd: Reg, nzuimm: u16 },
21    /// C.LW  rd' = sext(mem32\[rs1' + uimm])
22    CLw { rd: Reg, rs1: Reg, uimm: u8 },
23    /// C.SW  mem32\[rs1' + uimm] = rs2'
24    CSw { rs1: Reg, rs2: Reg, uimm: u8 },
25
26    // Quadrant 01
27    /// C.NOP  (ADDI x0, x0, 0 with rd==x0 and nzimm==0)
28    CNop,
29    /// C.ADDI  rd += nzimm  (rd != x0)
30    CAddi { rd: Reg, nzimm: i8 },
31    /// C.JAL  ra = pc+2; pc += imm
32    CJal { imm: i16 },
33    /// C.LI  rd = sext(imm)  (rd=x0 is a HINT)
34    CLi { rd: Reg, imm: i8 },
35    /// C.ADDI16SP  sp += nzimm  (nzimm != 0)
36    CAddi16sp { nzimm: i16 },
37    /// C.LUI  rd = sext(nzimm << 12)  (rd != x0, rd != x2, nzimm != 0)
38    CLui { rd: Reg, nzimm: I24 },
39    /// C.SRLI  rd' >>= shamt  (logical, 5-bit shamt; shamt=0 is a HINT)
40    CSrli { rd: Reg, shamt: u8 },
41    /// C.SRAI  rd' >>= shamt  (arithmetic, 5-bit shamt; shamt=0 is a HINT)
42    CSrai { rd: Reg, shamt: u8 },
43    /// C.ANDI  rd' &= sext(imm)
44    CAndi { rd: Reg, imm: i8 },
45    /// C.SUB  rd' -= rs2'
46    CSub { rd: Reg, rs2: Reg },
47    /// C.XOR  rd' ^= rs2'
48    CXor { rd: Reg, rs2: Reg },
49    /// C.OR   rd' |= rs2'
50    COr { rd: Reg, rs2: Reg },
51    /// C.AND  rd' &= rs2'
52    CAnd { rd: Reg, rs2: Reg },
53    /// C.J  pc += sext(imm)
54    CJ { imm: i16 },
55    /// C.BEQZ  if rs1' == 0: pc += sext(imm)
56    CBeqz { rs1: Reg, imm: i16 },
57    /// C.BNEZ  if rs1' != 0: pc += sext(imm)
58    CBnez { rs1: Reg, imm: i16 },
59
60    // Quadrant 10
61    /// C.SLLI  rd <<= shamt  (5-bit shamt; rd=x0 or shamt=0 is a HINT)
62    CSlli { rd: Reg, shamt: u8 },
63    /// C.LWSP  rd = sext(mem32\[sp + uimm])  (rd != x0)
64    CLwsp { rd: Reg, uimm: u8 },
65    /// C.JR  pc = rs1  (rs1 != x0)
66    CJr { rs1: Reg },
67    /// C.MV  rd = rs2  (rs2 != x0; rd=x0 is a HINT)
68    CMv { rd: Reg, rs2: Reg },
69    /// C.EBREAK
70    CEbreak,
71    /// C.JALR  ra = pc+2; pc = rs1  (rs1 != x0)
72    CJalr { rs1: Reg },
73    /// C.ADD  rd += rs2  (rs2 != x0; rd=x0 is a HINT)
74    CAdd { rd: Reg, rs2: Reg },
75    /// C.SWSP  mem32\[sp + uimm] = rs2
76    CSwsp { rs2: Reg, uimm: u8 },
77
78    // Unimplemented/illegal
79    CUnimp,
80}
81
82#[instruction]
83const impl<Reg> Instruction for Rv32ZcaInstruction<Reg>
84where
85    Reg: [const] Register<Type = u32>,
86{
87    type Reg = Reg;
88
89    #[inline(always)]
90    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
91    fn try_decode(instruction: u32) -> Option<Self> {
92        /// Map a 3-bit "prime" register field to an absolute register number
93        #[inline(always)]
94        const fn prime_reg_bits(bits: u8) -> u8 {
95            bits + 8
96        }
97
98        /// Reconstruct the CB-type branch offset used by C.BEQZ / C.BNEZ.
99        ///
100        /// Bit layout in the 16-bit instruction word:
101        /// ```text
102        ///   imm[8]   = inst[12]
103        ///   imm[4:3] = inst[11:10]
104        ///   imm[7:6] = inst[6:5]
105        ///   imm[2:1] = inst[4:3]
106        ///   imm[5]   = inst[2]
107        /// imm[0] is always 0 (2-byte aligned).
108        /// ```
109        #[inline(always)]
110        const fn decode_cb_branch_imm(inst: u16) -> i16 {
111            let imm8 = ((inst >> 12u8) & 1).cast_signed();
112            let imm4_3 = ((inst >> 10u8) & 0b11).cast_signed();
113            let imm7_6 = ((inst >> 5u8) & 0b11).cast_signed();
114            let imm2_1 = ((inst >> 3u8) & 0b11).cast_signed();
115            let imm5 = ((inst >> 2u8) & 1).cast_signed();
116            let raw =
117                (imm8 << 8u8) | (imm7_6 << 6u8) | (imm5 << 5u8) | (imm4_3 << 3u8) | (imm2_1 << 1u8);
118            // Sign-extend from bit 8 (9-bit immediate -> i16)
119            (raw << 7u8) >> 7u8
120        }
121
122        /// Decode CJ-type jump offset (C.J / C.JAL).
123        ///
124        /// Bit layout:
125        /// ```text
126        ///   imm[11]  = inst[12]
127        ///   imm[4]   = inst[11]
128        ///   imm[9:8] = inst[10:9]
129        ///   imm[10]  = inst[8]
130        ///   imm[6]   = inst[7]
131        ///   imm[7]   = inst[6]
132        ///   imm[3:1] = inst[5:3]
133        ///   imm[5]   = inst[2]
134        /// imm[0] is always 0 (2-byte aligned).
135        /// ```
136        #[inline(always)]
137        const fn decode_cj_imm(inst: u16) -> i16 {
138            let imm11 = ((inst >> 12u8) & 1).cast_signed();
139            let imm4 = ((inst >> 11u8) & 1).cast_signed();
140            let imm9_8 = ((inst >> 9u8) & 0b11).cast_signed();
141            let imm10 = ((inst >> 8u8) & 1).cast_signed();
142            let imm6 = ((inst >> 7u8) & 1).cast_signed();
143            let imm7 = ((inst >> 6u8) & 1).cast_signed();
144            let imm3_1 = ((inst >> 3u8) & 0b111).cast_signed();
145            let imm5 = ((inst >> 2u8) & 1).cast_signed();
146            let raw = (imm11 << 11u8)
147                | (imm10 << 10u8)
148                | (imm9_8 << 8u8)
149                | (imm7 << 7u8)
150                | (imm6 << 6u8)
151                | (imm5 << 5u8)
152                | (imm4 << 4u8)
153                | (imm3_1 << 1u8);
154            // Sign-extend from bit 11 (12-bit immediate -> i16)
155            (raw << 4u8) >> 4u8
156        }
157
158        let inst = instruction as u16;
159        let quadrant = inst & 0b11;
160        let funct3 = ((inst >> 13u8) & 0b111) as u8;
161
162        match quadrant {
163            // Quadrant 00
164            0b00 => match funct3 {
165                // C.ADDI4SPN
166                // nzuimm[5:4]  = inst[12:11]
167                // nzuimm[9:6]  = inst[10:7]
168                // nzuimm[2]    = inst[6]
169                // nzuimm[3]    = inst[5]
170                0b000 => {
171                    let imm5_4 = (inst >> 11u8) & 0b11;
172                    let imm9_6 = (inst >> 7u8) & 0xf;
173                    let imm2 = (inst >> 6u8) & 1;
174                    let imm3 = (inst >> 5u8) & 1;
175                    let nzuimm = (imm9_6 << 6u8) | (imm5_4 << 4u8) | (imm3 << 3u8) | (imm2 << 2u8);
176                    if nzuimm == 0 {
177                        if inst == 0 {
178                            Some(Self::CUnimp)
179                        } else {
180                            // Reserved encoding
181                            None
182                        }
183                    } else {
184                        let rd_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
185                        let rd = Reg::from_bits(rd_bits)?;
186                        Some(Self::CAddi4spn { rd, nzuimm })
187                    }
188                }
189                // C.LW
190                // uimm[5:3] = inst[12:10], uimm[2] = inst[6], uimm[6] = inst[5]
191                0b010 => {
192                    let uimm5_3 = ((inst >> 10u8) & 0b111) as u8;
193                    let uimm2 = ((inst >> 6u8) & 1) as u8;
194                    let uimm6 = ((inst >> 5u8) & 1) as u8;
195                    let uimm = (uimm6 << 6u8) | (uimm5_3 << 3u8) | (uimm2 << 2u8);
196                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
197                    let rd_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
198                    let rs1 = Reg::from_bits(rs1_bits)?;
199                    let rd = Reg::from_bits(rd_bits)?;
200                    Some(Self::CLw { rd, rs1, uimm })
201                }
202                // C.SW  (same uimm layout as C.LW)
203                0b110 => {
204                    let uimm5_3 = ((inst >> 10u8) & 0b111) as u8;
205                    let uimm2 = ((inst >> 6u8) & 1) as u8;
206                    let uimm6 = ((inst >> 5u8) & 1) as u8;
207                    let uimm = (uimm6 << 6u8) | (uimm5_3 << 3u8) | (uimm2 << 2u8);
208                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
209                    let rs2_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
210                    let rs1 = Reg::from_bits(rs1_bits)?;
211                    let rs2 = Reg::from_bits(rs2_bits)?;
212                    Some(Self::CSw { rs1, rs2, uimm })
213                }
214                // funct3=001: C.FLD (Zcd) - not in Zca, reserved
215                // funct3=011: C.FLD (Zcd) - not in Zca, reserved
216                // funct3=100: used by Zcb
217                // funct3=101: C.FSD (Zcd) - not in Zca, reserved
218                // funct3=111: C.FSD (Zcd) - not in Zca, reserved
219                _ => None,
220            },
221
222            // Quadrant 01
223            0b01 => match funct3 {
224                // C.NOP (rd=x0) / C.ADDI (rd!=x0)
225                // nzimm[5] = inst[12], nzimm[4:0] = inst[6:2]
226                0b000 => {
227                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
228                    let imm5 = ((inst >> 12u8) & 1) as u8;
229                    let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
230                    let imm_raw = (imm5 << 5u8) | imm4_0;
231                    // Sign-extend 6-bit immediate to i8
232                    let nzimm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
233                    if rd_bits == 0 && nzimm == 0 {
234                        Some(Self::CNop)
235                    } else {
236                        let rd = Reg::from_bits(rd_bits)?;
237                        Some(Self::CAddi { rd, nzimm })
238                    }
239                }
240                // C.JAL  (same CJ immediate encoding as C.J)
241                0b001 => Some(Self::CJal {
242                    imm: decode_cj_imm(inst),
243                }),
244                // C.LI  rd = sext(imm)  (rd=x0 is a HINT, still decoded)
245                // imm[5] = inst[12], imm[4:0] = inst[6:2]
246                0b010 => {
247                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
248                    let rd = Reg::from_bits(rd_bits)?;
249                    let imm5 = ((inst >> 12u8) & 1) as u8;
250                    let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
251                    let imm_raw = (imm5 << 5u8) | imm4_0;
252                    let imm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
253                    Some(Self::CLi { rd, imm })
254                }
255                // C.ADDI16SP (rd=x2) / C.LUI (rd!=x0, rd!=x2)
256                0b011 => {
257                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
258                    if rd_bits == 2 {
259                        // C.ADDI16SP
260                        // nzimm[9]   = inst[12]
261                        // nzimm[4]   = inst[6]
262                        // nzimm[6]   = inst[5]
263                        // nzimm[8:7] = inst[4:3]
264                        // nzimm[5]   = inst[2]
265                        let imm9 = ((inst >> 12u8) & 1).cast_signed();
266                        let imm4 = ((inst >> 6u8) & 1).cast_signed();
267                        let imm6 = ((inst >> 5u8) & 1).cast_signed();
268                        let imm8_7 = ((inst >> 3u8) & 0b11).cast_signed();
269                        let imm5 = ((inst >> 2u8) & 1).cast_signed();
270                        let raw = (imm9 << 9u8)
271                            | (imm8_7 << 7u8)
272                            | (imm6 << 6u8)
273                            | (imm5 << 5u8)
274                            | (imm4 << 4u8);
275                        if raw == 0 {
276                            None?;
277                        }
278                        // Sign-extend from bit 9 (10-bit nzimm -> i16)
279                        let nzimm = (raw << 6u8) >> 6u8;
280                        Some(Self::CAddi16sp { nzimm })
281                    } else {
282                        // C.LUI (rd=x0 is a hint, still decoded)
283                        let rd = Reg::from_bits(rd_bits)?;
284                        // nzimm[17]    = inst[12]
285                        // nzimm[16:12] = inst[6:2]
286                        let imm17 = ((inst >> 12u8) & 1) as i32;
287                        let imm16_12 = ((inst >> 2u8) & 0x1f) as i32;
288                        let raw = (imm17 << 17u8) | (imm16_12 << 12u8);
289                        if raw == 0 {
290                            None?;
291                        }
292                        // Sign-extend from bit 17 (18-bit nzimm -> i32)
293                        let nzimm = I24::from_i32((raw << 14u8) >> 14u8);
294                        Some(Self::CLui { rd, nzimm })
295                    }
296                }
297                // C.SRLI / C.SRAI / C.ANDI / arithmetic
298                // RV32: shamt is 5-bit only (inst[12] must be 0 for shifts, else reserved)
299                0b100 => {
300                    let funct2 = ((inst >> 10u8) & 0b11) as u8;
301                    let rd_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
302                    match funct2 {
303                        // C.SRLI  shamt[4:0]=inst[6:2]
304                        // RV32: shamt[5]=inst[12] must be 0, else reserved (NSE)
305                        // shamt=0 is a HINT, still decoded
306                        0b00 => {
307                            let rd = Reg::from_bits(rd_bits)?;
308                            let shamt5 = ((inst >> 12u8) & 1) as u8;
309                            let shamt40 = ((inst >> 2u8) & 0x1f) as u8;
310                            if shamt5 != 0 {
311                                None?;
312                            }
313                            Some(Self::CSrli { rd, shamt: shamt40 })
314                        }
315                        // C.SRAI  (same shamt layout as C.SRLI)
316                        // RV32: shamt[5]=inst[12] must be 0, else reserved (NSE)
317                        // shamt=0 is a HINT, still decoded
318                        0b01 => {
319                            let rd = Reg::from_bits(rd_bits)?;
320                            let shamt5 = ((inst >> 12u8) & 1) as u8;
321                            let shamt40 = ((inst >> 2u8) & 0x1f) as u8;
322                            if shamt5 != 0 {
323                                None?;
324                            }
325                            Some(Self::CSrai { rd, shamt: shamt40 })
326                        }
327                        // C.ANDI  imm[5]=inst[12], imm[4:0]=inst[6:2]
328                        0b10 => {
329                            let rd = Reg::from_bits(rd_bits)?;
330                            let imm5 = ((inst >> 12u8) & 1) as u8;
331                            let imm4_0 = ((inst >> 2u8) & 0x1f) as u8;
332                            let imm_raw = (imm5 << 5u8) | imm4_0;
333                            let imm = ((imm_raw.cast_signed()) << 2u8) >> 2u8;
334                            Some(Self::CAndi { rd, imm })
335                        }
336                        // Arithmetic: only bit12=0 variants valid in RV32
337                        // bit12=1 (C.SUBW/C.ADDW) does not exist in RV32, reserved
338                        0b11 => {
339                            let bit12 = (inst >> 12u8) & 1;
340                            if bit12 != 0 {
341                                None?;
342                            }
343                            let funct2b = ((inst >> 5u8) & 0b11) as u8;
344                            let rs2_bits = prime_reg_bits(((inst >> 2u8) & 0b111) as u8);
345                            let rd = Reg::from_bits(rd_bits)?;
346                            let rs2 = Reg::from_bits(rs2_bits)?;
347                            match funct2b {
348                                0b00 => Some(Self::CSub { rd, rs2 }),
349                                0b01 => Some(Self::CXor { rd, rs2 }),
350                                0b10 => Some(Self::COr { rd, rs2 }),
351                                0b11 => Some(Self::CAnd { rd, rs2 }),
352                                _ => None,
353                            }
354                        }
355                        _ => None,
356                    }
357                }
358                // C.J
359                0b101 => Some(Self::CJ {
360                    imm: decode_cj_imm(inst),
361                }),
362                // C.BEQZ
363                0b110 => {
364                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
365                    let rs1 = Reg::from_bits(rs1_bits)?;
366                    Some(Self::CBeqz {
367                        rs1,
368                        imm: decode_cb_branch_imm(inst),
369                    })
370                }
371                // C.BNEZ
372                0b111 => {
373                    let rs1_bits = prime_reg_bits(((inst >> 7u8) & 0b111) as u8);
374                    let rs1 = Reg::from_bits(rs1_bits)?;
375                    Some(Self::CBnez {
376                        rs1,
377                        imm: decode_cb_branch_imm(inst),
378                    })
379                }
380                _ => None,
381            },
382
383            // Quadrant 10
384            0b10 => match funct3 {
385                // C.SLLI  shamt[4:0]=inst[6:2]
386                // RV32: shamt[5]=inst[12] must be 0, else reserved (NSE)
387                // rd=x0 or shamt=0 is a HINT, still decoded
388                0b000 => {
389                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
390                    let rd = Reg::from_bits(rd_bits)?;
391                    let shamt5 = ((inst >> 12u8) & 1) as u8;
392                    let shamt40 = ((inst >> 2u8) & 0x1f) as u8;
393                    if shamt5 != 0 {
394                        None?;
395                    }
396                    Some(Self::CSlli { rd, shamt: shamt40 })
397                }
398                // C.LWSP  uimm[5]=inst[12], uimm[4:2]=inst[6:4], uimm[7:6]=inst[3:2]
399                // rd=x0 is reserved
400                0b010 => {
401                    let rd_bits = ((inst >> 7u8) & 0x1f) as u8;
402                    if rd_bits == 0 {
403                        None?;
404                    }
405                    let rd = Reg::from_bits(rd_bits)?;
406                    let uimm5 = ((inst >> 12u8) & 1) as u8;
407                    let uimm42 = ((inst >> 4u8) & 0b111) as u8;
408                    let uimm76 = ((inst >> 2u8) & 0b11) as u8;
409                    let uimm = (uimm76 << 6u8) | (uimm5 << 5u8) | (uimm42 << 2u8);
410                    Some(Self::CLwsp { rd, uimm })
411                }
412                // funct3=001: C.FLWSP (Zcf, not Zca) - reserved
413                // funct3=011: C.FLDSP (Zcd, not Zca) - reserved
414                // C.JR / C.MV / C.EBREAK / C.JALR / C.ADD
415                0b100 => {
416                    let rs1_bits = ((inst >> 7u8) & 0x1f) as u8;
417                    let rs2_bits = ((inst >> 2u8) & 0x1f) as u8;
418                    let bit12 = (inst >> 12u8) & 1;
419                    if bit12 == 0 {
420                        if rs2_bits == 0 {
421                            // C.JR  (rs1=x0 is reserved)
422                            if rs1_bits == 0 {
423                                None?;
424                            }
425                            let rs1 = Reg::from_bits(rs1_bits)?;
426                            Some(Self::CJr { rs1 })
427                        } else {
428                            // C.MV  (rs2!=x0; rd=x0 is a HINT, still decoded)
429                            let rd = Reg::from_bits(rs1_bits)?;
430                            let rs2 = Reg::from_bits(rs2_bits)?;
431                            Some(Self::CMv { rd, rs2 })
432                        }
433                    } else if rs2_bits == 0 {
434                        if rs1_bits == 0 {
435                            // C.EBREAK
436                            Some(Self::CEbreak)
437                        } else {
438                            // C.JALR  (rs1!=x0)
439                            let rs1 = Reg::from_bits(rs1_bits)?;
440                            Some(Self::CJalr { rs1 })
441                        }
442                    } else {
443                        // C.ADD  (rs2!=x0; rd=x0 is a HINT, still decoded)
444                        let rd = Reg::from_bits(rs1_bits)?;
445                        let rs2 = Reg::from_bits(rs2_bits)?;
446                        Some(Self::CAdd { rd, rs2 })
447                    }
448                }
449                // C.SWSP  uimm[5:2]=inst[12:9], uimm[7:6]=inst[8:7]
450                0b110 => {
451                    let rs2_bits = ((inst >> 2u8) & 0x1f) as u8;
452                    let rs2 = Reg::from_bits(rs2_bits)?;
453                    let uimm52 = ((inst >> 9u8) & 0xf) as u8;
454                    let uimm76 = ((inst >> 7u8) & 0b11) as u8;
455                    let uimm = (uimm76 << 6u8) | (uimm52 << 2u8);
456                    Some(Self::CSwsp { rs2, uimm })
457                }
458                // funct3=111: C.FSWSP (Zcf, not Zca) - reserved
459                _ => None,
460            },
461
462            // Quadrant 11 = 32-bit instructions
463            _ => None,
464        }
465    }
466
467    #[inline(always)]
468    fn alignment() -> u8 {
469        align_of::<u16>() as u8
470    }
471
472    #[inline(always)]
473    fn size(&self) -> u8 {
474        size_of::<u16>() as u8
475    }
476}
477
478#[instruction]
479impl<Reg> fmt::Display for Rv32ZcaInstruction<Reg>
480where
481    Reg: fmt::Display,
482{
483    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
484        match self {
485            Self::CAddi4spn { rd, nzuimm } => write!(f, "c.addi4spn {rd}, sp, {nzuimm}"),
486            Self::CLw { rd, rs1, uimm } => write!(f, "c.lw {rd}, {uimm}({rs1})"),
487            Self::CSw { rs1, rs2, uimm } => write!(f, "c.sw {rs2}, {uimm}({rs1})"),
488            Self::CNop => write!(f, "c.nop"),
489            Self::CAddi { rd, nzimm } => write!(f, "c.addi {rd}, {nzimm}"),
490            Self::CJal { imm } => write!(f, "c.jal {imm}"),
491            Self::CLi { rd, imm } => write!(f, "c.li {rd}, {imm}"),
492            Self::CAddi16sp { nzimm } => write!(f, "c.addi16sp sp, {nzimm}"),
493            Self::CLui { rd, nzimm } => write!(f, "c.lui {rd}, 0x{:x}", nzimm >> 12u8),
494            Self::CSrli { rd, shamt } => write!(f, "c.srli {rd}, {shamt}"),
495            Self::CSrai { rd, shamt } => write!(f, "c.srai {rd}, {shamt}"),
496            Self::CAndi { rd, imm } => write!(f, "c.andi {rd}, {imm}"),
497            Self::CSub { rd, rs2 } => write!(f, "c.sub {rd}, {rs2}"),
498            Self::CXor { rd, rs2 } => write!(f, "c.xor {rd}, {rs2}"),
499            Self::COr { rd, rs2 } => write!(f, "c.or {rd}, {rs2}"),
500            Self::CAnd { rd, rs2 } => write!(f, "c.and {rd}, {rs2}"),
501            Self::CJ { imm } => write!(f, "c.j {imm}"),
502            Self::CBeqz { rs1, imm } => write!(f, "c.beqz {rs1}, {imm}"),
503            Self::CBnez { rs1, imm } => write!(f, "c.bnez {rs1}, {imm}"),
504            Self::CSlli { rd, shamt } => write!(f, "c.slli {rd}, {shamt}"),
505            Self::CLwsp { rd, uimm } => write!(f, "c.lwsp {rd}, {uimm}(sp)"),
506            Self::CJr { rs1 } => write!(f, "c.jr {rs1}"),
507            Self::CMv { rd, rs2 } => write!(f, "c.mv {rd}, {rs2}"),
508            Self::CEbreak => write!(f, "c.ebreak"),
509            Self::CJalr { rs1 } => write!(f, "c.jalr {rs1}"),
510            Self::CAdd { rd, rs2 } => write!(f, "c.add {rd}, {rs2}"),
511            Self::CSwsp { rs2, uimm } => write!(f, "c.swsp {rs2}, {uimm}(sp)"),
512            Self::CUnimp => write!(f, "c.unimp"),
513        }
514    }
515}