ab_riscv_primitives/instructions/rv32/b/
zbs.rs

1//! RV32 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zbs instruction (Single-bit instructions)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum Rv32ZbsInstruction<Reg> {
16    // Single-Bit Set
17    Bset { rd: Reg, rs1: Reg, rs2: Reg },
18    Bseti { rd: Reg, rs1: Reg, shamt: u8 },
19
20    // Single-Bit Clear
21    Bclr { rd: Reg, rs1: Reg, rs2: Reg },
22    Bclri { rd: Reg, rs1: Reg, shamt: u8 },
23
24    // Single-Bit Invert
25    Binv { rd: Reg, rs1: Reg, rs2: Reg },
26    Binvi { rd: Reg, rs1: Reg, shamt: u8 },
27
28    // Single-Bit Extract
29    Bext { rd: Reg, rs1: Reg, rs2: Reg },
30    Bexti { rd: Reg, rs1: Reg, shamt: u8 },
31}
32
33#[instruction]
34const impl<Reg> Instruction for Rv32ZbsInstruction<Reg>
35where
36    Reg: [const] Register<Type = u32>,
37{
38    const ALIGNMENT: u8 = align_of::<u32>() as u8;
39
40    type Reg = Reg;
41
42    #[inline(always)]
43    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
44    fn try_decode(instruction: u32) -> Option<Self> {
45        let opcode = (instruction & 0b111_1111) as u8;
46        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
47        let funct3 = ((instruction >> 12) & 0b111) as u8;
48        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
49        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
50        let shamt = ((instruction >> 20) & 0x1f) as u8;
51        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
52
53        match opcode {
54            // R-type instructions
55            0b011_0011 => {
56                let rd = Reg::from_bits(rd_bits)?;
57                let rs1 = Reg::from_bits(rs1_bits)?;
58                let rs2 = Reg::from_bits(rs2_bits)?;
59                match (funct3, funct7) {
60                    (0b001, 0b001_0100) => Some(Self::Bset { rd, rs1, rs2 }),
61                    (0b001, 0b010_0100) => Some(Self::Bclr { rd, rs1, rs2 }),
62                    (0b001, 0b011_0100) => Some(Self::Binv { rd, rs1, rs2 }),
63                    (0b101, 0b010_0100) => Some(Self::Bext { rd, rs1, rs2 }),
64                    _ => None,
65                }
66            }
67            // I-type instructions
68            0b001_0011 => {
69                let rd = Reg::from_bits(rd_bits)?;
70                let rs1 = Reg::from_bits(rs1_bits)?;
71                match (funct3, funct7) {
72                    (0b001, 0b001_0100) => Some(Self::Bseti { rd, rs1, shamt }),
73                    (0b001, 0b010_0100) => Some(Self::Bclri { rd, rs1, shamt }),
74                    (0b001, 0b011_0100) => Some(Self::Binvi { rd, rs1, shamt }),
75                    (0b101, 0b010_0100) => Some(Self::Bexti { rd, rs1, shamt }),
76                    _ => None,
77                }
78            }
79            _ => None,
80        }
81    }
82
83    #[inline(always)]
84    fn size(&self) -> u8 {
85        size_of::<u32>() as u8
86    }
87}
88
89#[instruction]
90impl<Reg> fmt::Display for Rv32ZbsInstruction<Reg>
91where
92    Reg: fmt::Display,
93{
94    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
95        match self {
96            Self::Bset { rd, rs1, rs2 } => write!(f, "bset {rd}, {rs1}, {rs2}"),
97            Self::Bseti { rd, rs1, shamt } => write!(f, "bseti {rd}, {rs1}, {shamt}"),
98            Self::Bclr { rd, rs1, rs2 } => write!(f, "bclr {rd}, {rs1}, {rs2}"),
99            Self::Bclri { rd, rs1, shamt } => write!(f, "bclri {rd}, {rs1}, {shamt}"),
100            Self::Binv { rd, rs1, rs2 } => write!(f, "binv {rd}, {rs1}, {rs2}"),
101            Self::Binvi { rd, rs1, shamt } => write!(f, "binvi {rd}, {rs1}, {shamt}"),
102            Self::Bext { rd, rs1, rs2 } => write!(f, "bext {rd}, {rs1}, {rs2}"),
103            Self::Bexti { rd, rs1, shamt } => write!(f, "bexti {rd}, {rs1}, {shamt}"),
104        }
105    }
106}
ab_riscv_primitives/instructions/rv32/b/zbs.rs

ab_riscv_primitives/instructions/rv32/b/
zbs.rs
