ab_riscv_primitives/instructions/rv32/b/
zbs.rs

1//! RV32 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zbs instruction (Single-bit instructions)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv32ZbsInstruction<Reg> {
15    // Single-Bit Set
16    Bset { rd: Reg, rs1: Reg, rs2: Reg },
17    Bseti { rd: Reg, rs1: Reg, shamt: u8 },
18
19    // Single-Bit Clear
20    Bclr { rd: Reg, rs1: Reg, rs2: Reg },
21    Bclri { rd: Reg, rs1: Reg, shamt: u8 },
22
23    // Single-Bit Invert
24    Binv { rd: Reg, rs1: Reg, rs2: Reg },
25    Binvi { rd: Reg, rs1: Reg, shamt: u8 },
26
27    // Single-Bit Extract
28    Bext { rd: Reg, rs1: Reg, rs2: Reg },
29    Bexti { rd: Reg, rs1: Reg, shamt: u8 },
30}
31
32#[instruction]
33impl<Reg> const Instruction for Rv32ZbsInstruction<Reg>
34where
35    Reg: [const] Register<Type = u32>,
36{
37    type Reg = Reg;
38
39    #[inline(always)]
40    fn try_decode(instruction: u32) -> Option<Self> {
41        let opcode = (instruction & 0b111_1111) as u8;
42        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
43        let funct3 = ((instruction >> 12) & 0b111) as u8;
44        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
45        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
46        let shamt = ((instruction >> 20) & 0x1f) as u8;
47        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
48
49        match opcode {
50            // R-type instructions
51            0b0110011 => {
52                let rd = Reg::from_bits(rd_bits)?;
53                let rs1 = Reg::from_bits(rs1_bits)?;
54                let rs2 = Reg::from_bits(rs2_bits)?;
55                match (funct3, funct7) {
56                    (0b001, 0b0010100) => Some(Self::Bset { rd, rs1, rs2 }),
57                    (0b001, 0b0100100) => Some(Self::Bclr { rd, rs1, rs2 }),
58                    (0b001, 0b0110100) => Some(Self::Binv { rd, rs1, rs2 }),
59                    (0b101, 0b0100100) => Some(Self::Bext { rd, rs1, rs2 }),
60                    _ => None,
61                }
62            }
63            // I-type instructions
64            0b0010011 => {
65                let rd = Reg::from_bits(rd_bits)?;
66                let rs1 = Reg::from_bits(rs1_bits)?;
67                match (funct3, funct7) {
68                    (0b001, 0b0010100) => Some(Self::Bseti { rd, rs1, shamt }),
69                    (0b001, 0b0100100) => Some(Self::Bclri { rd, rs1, shamt }),
70                    (0b001, 0b0110100) => Some(Self::Binvi { rd, rs1, shamt }),
71                    (0b101, 0b0100100) => Some(Self::Bexti { rd, rs1, shamt }),
72                    _ => None,
73                }
74            }
75            _ => None,
76        }
77    }
78
79    #[inline(always)]
80    fn alignment() -> u8 {
81        size_of::<u32>() as u8
82    }
83
84    #[inline(always)]
85    fn size(&self) -> u8 {
86        size_of::<u32>() as u8
87    }
88}
89
90impl<Reg> fmt::Display for Rv32ZbsInstruction<Reg>
91where
92    Reg: fmt::Display,
93{
94    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
95        match self {
96            Self::Bset { rd, rs1, rs2 } => write!(f, "bset {}, {}, {}", rd, rs1, rs2),
97            Self::Bseti { rd, rs1, shamt } => write!(f, "bseti {}, {}, {}", rd, rs1, shamt),
98            Self::Bclr { rd, rs1, rs2 } => write!(f, "bclr {}, {}, {}", rd, rs1, rs2),
99            Self::Bclri { rd, rs1, shamt } => write!(f, "bclri {}, {}, {}", rd, rs1, shamt),
100            Self::Binv { rd, rs1, rs2 } => write!(f, "binv {}, {}, {}", rd, rs1, rs2),
101            Self::Binvi { rd, rs1, shamt } => write!(f, "binvi {}, {}, {}", rd, rs1, shamt),
102            Self::Bext { rd, rs1, rs2 } => write!(f, "bext {}, {}, {}", rd, rs1, rs2),
103            Self::Bexti { rd, rs1, shamt } => write!(f, "bexti {}, {}, {}", rd, rs1, shamt),
104        }
105    }
106}
ab_riscv_primitives/instructions/rv32/b/zbs.rs

ab_riscv_primitives/instructions/rv32/b/
zbs.rs
