ab_riscv_primitives/instructions/rv32/b/
zbc.rs

1//! RV32 Zbc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::rv32::zk::zbkc::Rv32ZbkcInstruction;
8use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
9use crate::registers::general_purpose::Register;
10use ab_riscv_macros::instruction;
11use core::fmt;
12
13/// RISC-V RV32 Zbc instruction (Carryless multiplication)
14#[instruction(inherit = [Rv32ZbkcInstruction])]
15#[derive(Debug, Clone, Copy)]
16#[derive_const(PartialEq, Eq)]
17#[rustfmt::skip]
18pub enum Rv32ZbcInstruction<Hart>
19where
20    Hart: HartConfig,
21{
22    Clmulr { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
23}
24
25#[instruction]
26const impl<Reg, Hart> Instruction for Rv32ZbcInstruction<Hart>
27where
28    Reg: [const] Register<Type = u32>,
29    Hart: [const] HartConfig<Reg = Reg>,
30{
31    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zbc", 1, 0)];
32
33    const ALIGNMENT: u8 = align_of::<u32>() as u8;
34
35    type Hart = Hart;
36
37    #[inline(always)]
38    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
39    fn try_decode(instruction: u32) -> Option<Self> {
40        let opcode = (instruction & 0b111_1111) as u8;
41        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
42        let funct3 = ((instruction >> 12) & 0b111) as u8;
43        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
44        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
45        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
46
47        match opcode {
48            // R-type
49            0b011_0011 => {
50                let rd = Reg::from_bits(rd_bits)?;
51                let rs1 = Reg::from_bits(rs1_bits)?;
52                let rs2 = Reg::from_bits(rs2_bits)?;
53                match (funct3, funct7) {
54                    (0b010, 0b000_0101) => Some(Self::Clmulr { rd, rs1, rs2 }),
55                    _ => None,
56                }
57            }
58            _ => None,
59        }
60    }
61
62    #[inline(always)]
63    fn size(&self) -> u8 {
64        size_of::<u32>() as u8
65    }
66}
67
68#[instruction]
69impl<Reg, Hart> fmt::Display for Rv32ZbcInstruction<Hart>
70where
71    Reg: fmt::Display + Copy,
72    Hart: HartConfig<Reg = Reg>,
73{
74    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
75        match self {
76            Self::Clmulr { rd, rs1, rs2 } => write!(f, "clmulr {rd}, {rs1}, {rs2}"),
77        }
78    }
79}
ab_riscv_primitives/instructions/rv32/b/zbc.rs

ab_riscv_primitives/instructions/rv32/b/
zbc.rs
