ab_riscv_primitives/instructions/rv32/b/
zbb.rs

1//! RV32 Zbb extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zbb instruction (Basic bit manipulation)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum Rv32ZbbInstruction<Reg> {
16    Andn { rd: Reg, rs1: Reg, rs2: Reg },
17    Orn { rd: Reg, rs1: Reg, rs2: Reg },
18    Xnor { rd: Reg, rs1: Reg, rs2: Reg },
19    Clz { rd: Reg, rs1: Reg },
20    Ctz { rd: Reg, rs1: Reg },
21    Cpop { rd: Reg, rs1: Reg },
22    Max { rd: Reg, rs1: Reg, rs2: Reg },
23    Maxu { rd: Reg, rs1: Reg, rs2: Reg },
24    Min { rd: Reg, rs1: Reg, rs2: Reg },
25    Minu { rd: Reg, rs1: Reg, rs2: Reg },
26    Sextb { rd: Reg, rs1: Reg },
27    Sexth { rd: Reg, rs1: Reg },
28    Zexth { rd: Reg, rs1: Reg },
29    Rol { rd: Reg, rs1: Reg, rs2: Reg },
30    Ror { rd: Reg, rs1: Reg, rs2: Reg },
31    Rori { rd: Reg, rs1: Reg, shamt: u8 },
32    Orcb { rd: Reg, rs1: Reg },
33    Rev8 { rd: Reg, rs1: Reg },
34}
35
36#[instruction]
37const impl<Reg> Instruction for Rv32ZbbInstruction<Reg>
38where
39    Reg: [const] Register<Type = u32>,
40{
41    type Reg = Reg;
42
43    #[inline(always)]
44    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
45    fn try_decode(instruction: u32) -> Option<Self> {
46        let opcode = (instruction & 0b111_1111) as u8;
47        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
48        let funct3 = ((instruction >> 12) & 0b111) as u8;
49        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
50        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
51        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
52        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
53        // For I-type: bits [25:20]
54        let low5 = ((instruction >> 20) & 0x1f) as u8;
55        let funct12 = ((instruction >> 20) & 0xfff) as u16;
56
57        match opcode {
58            // OP-IMM
59            0b001_0011 => {
60                let rd = Reg::from_bits(rd_bits)?;
61                let rs1 = Reg::from_bits(rs1_bits)?;
62                match funct3 {
63                    0b001 => {
64                        // RV32: shamt is 5 bits; funct7 distinguishes the operation
65                        if funct7 == 0b011_0000 {
66                            match rs2_bits {
67                                0 => Some(Self::Clz { rd, rs1 }),
68                                1 => Some(Self::Ctz { rd, rs1 }),
69                                2 => Some(Self::Cpop { rd, rs1 }),
70                                4 => Some(Self::Sextb { rd, rs1 }),
71                                5 => Some(Self::Sexth { rd, rs1 }),
72                                _ => None,
73                            }
74                        } else {
75                            None
76                        }
77                    }
78                    0b101 => {
79                        // orc.b: funct12 = 0b0010_1000_0111
80                        // rev8 for RV32: funct12 = 0b0110_1001_1000
81                        // rori: funct6 = 0b01_1000, shamt in bits [24:20]
82                        if funct12 == 0b0010_1000_0111 {
83                            Some(Self::Orcb { rd, rs1 })
84                        } else if funct12 == 0b0110_1001_1000 {
85                            Some(Self::Rev8 { rd, rs1 })
86                        } else if funct6 == 0b01_1000 {
87                            Some(Self::Rori {
88                                rd,
89                                rs1,
90                                shamt: low5,
91                            })
92                        } else {
93                            None
94                        }
95                    }
96                    _ => None,
97                }
98            }
99            // OP / R-type
100            0b011_0011 => {
101                let rd = Reg::from_bits(rd_bits)?;
102                let rs1 = Reg::from_bits(rs1_bits)?;
103                let rs2 = Reg::from_bits(rs2_bits)?;
104                match funct3 {
105                    0b001 => {
106                        if funct7 == 0b011_0000 {
107                            Some(Self::Rol { rd, rs1, rs2 })
108                        } else {
109                            None
110                        }
111                    }
112                    0b100 => match funct7 {
113                        0b010_0000 => Some(Self::Xnor { rd, rs1, rs2 }),
114                        0b000_0101 => Some(Self::Min { rd, rs1, rs2 }),
115                        // zext.h for RV32 uses OP (0b011_0011), funct7=0b000_0100, rs2=0
116                        0b000_0100 => {
117                            if rs2_bits == 0 {
118                                Some(Self::Zexth { rd, rs1 })
119                            } else {
120                                None
121                            }
122                        }
123                        _ => None,
124                    },
125                    0b101 => match funct7 {
126                        0b011_0000 => Some(Self::Ror { rd, rs1, rs2 }),
127                        0b000_0101 => Some(Self::Minu { rd, rs1, rs2 }),
128                        _ => None,
129                    },
130                    0b110 => match funct7 {
131                        0b010_0000 => Some(Self::Orn { rd, rs1, rs2 }),
132                        0b000_0101 => Some(Self::Max { rd, rs1, rs2 }),
133                        _ => None,
134                    },
135                    0b111 => match funct7 {
136                        0b010_0000 => Some(Self::Andn { rd, rs1, rs2 }),
137                        0b000_0101 => Some(Self::Maxu { rd, rs1, rs2 }),
138                        _ => None,
139                    },
140                    _ => None,
141                }
142            }
143            _ => None,
144        }
145    }
146
147    #[inline(always)]
148    fn alignment() -> u8 {
149        align_of::<u32>() as u8
150    }
151
152    #[inline(always)]
153    fn size(&self) -> u8 {
154        size_of::<u32>() as u8
155    }
156}
157
158#[instruction]
159impl<Reg> fmt::Display for Rv32ZbbInstruction<Reg>
160where
161    Reg: fmt::Display,
162{
163    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
164        match self {
165            Self::Andn { rd, rs1, rs2 } => write!(f, "andn {rd}, {rs1}, {rs2}"),
166            Self::Orn { rd, rs1, rs2 } => write!(f, "orn {rd}, {rs1}, {rs2}"),
167            Self::Xnor { rd, rs1, rs2 } => write!(f, "xnor {rd}, {rs1}, {rs2}"),
168            Self::Clz { rd, rs1 } => write!(f, "clz {rd}, {rs1}"),
169            Self::Ctz { rd, rs1 } => write!(f, "ctz {rd}, {rs1}"),
170            Self::Cpop { rd, rs1 } => write!(f, "cpop {rd}, {rs1}"),
171            Self::Max { rd, rs1, rs2 } => write!(f, "max {rd}, {rs1}, {rs2}"),
172            Self::Maxu { rd, rs1, rs2 } => write!(f, "maxu {rd}, {rs1}, {rs2}"),
173            Self::Min { rd, rs1, rs2 } => write!(f, "min {rd}, {rs1}, {rs2}"),
174            Self::Minu { rd, rs1, rs2 } => write!(f, "minu {rd}, {rs1}, {rs2}"),
175            Self::Sextb { rd, rs1 } => write!(f, "sext.b {rd}, {rs1}"),
176            Self::Sexth { rd, rs1 } => write!(f, "sext.h {rd}, {rs1}"),
177            Self::Zexth { rd, rs1 } => write!(f, "zext.h {rd}, {rs1}"),
178            Self::Rol { rd, rs1, rs2 } => write!(f, "rol {rd}, {rs1}, {rs2}"),
179            Self::Ror { rd, rs1, rs2 } => write!(f, "ror {rd}, {rs1}, {rs2}"),
180            Self::Rori { rd, rs1, shamt } => write!(f, "rori {rd}, {rs1}, {shamt}"),
181            Self::Orcb { rd, rs1 } => write!(f, "orc.b {rd}, {rs1}"),
182            Self::Rev8 { rd, rs1 } => write!(f, "rev8 {rd}, {rs1}"),
183        }
184    }
185}
ab_riscv_primitives/instructions/rv32/b/zbb.rs

ab_riscv_primitives/instructions/rv32/b/
zbb.rs
