ab_riscv_primitives/instructions/rv32/b/
zba.rs

1//! RV32 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zba instruction (Address generation)
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv32ZbaInstruction<Hart>
18where
19    Hart: HartConfig,
20{
21    Sh1add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
22    Sh2add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
23    Sh3add { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg },
24}
25
26#[instruction]
27const impl<Reg, Hart> Instruction for Rv32ZbaInstruction<Hart>
28where
29    Reg: [const] Register<Type = u32>,
30    Hart: [const] HartConfig<Reg = Reg>,
31{
32    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zba", 1, 0)];
33
34    const ALIGNMENT: u8 = align_of::<u32>() as u8;
35
36    type Hart = Hart;
37
38    #[inline(always)]
39    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
40    fn try_decode(instruction: u32) -> Option<Self> {
41        let opcode = (instruction & 0b111_1111) as u8;
42        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
43        let funct3 = ((instruction >> 12) & 0b111) as u8;
44        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
45        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
46        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
47
48        match opcode {
49            // R-type
50            0b011_0011 => {
51                let rd = Reg::from_bits(rd_bits)?;
52                let rs1 = Reg::from_bits(rs1_bits)?;
53                let rs2 = Reg::from_bits(rs2_bits)?;
54                match (funct3, funct7) {
55                    (0b010, 0b001_0000) => Some(Self::Sh1add { rd, rs1, rs2 }),
56                    (0b100, 0b001_0000) => Some(Self::Sh2add { rd, rs1, rs2 }),
57                    (0b110, 0b001_0000) => Some(Self::Sh3add { rd, rs1, rs2 }),
58                    _ => None,
59                }
60            }
61            _ => None,
62        }
63    }
64
65    #[inline(always)]
66    fn size(&self) -> u8 {
67        size_of::<u32>() as u8
68    }
69}
70
71#[instruction]
72impl<Reg, Hart> fmt::Display for Rv32ZbaInstruction<Hart>
73where
74    Reg: fmt::Display,
75    Hart: HartConfig<Reg = Reg>,
76{
77    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
78        match self {
79            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {rd}, {rs1}, {rs2}"),
80            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {rd}, {rs1}, {rs2}"),
81            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {rd}, {rs1}, {rs2}"),
82        }
83    }
84}
ab_riscv_primitives/instructions/rv32/b/zba.rs

ab_riscv_primitives/instructions/rv32/b/
zba.rs
