ab_riscv_primitives/instructions/rv32/b/
zba.rs

1//! RV32 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zba instruction (Address generation)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15pub enum Rv32ZbaInstruction<Reg> {
16    Sh1add { rd: Reg, rs1: Reg, rs2: Reg },
17    Sh2add { rd: Reg, rs1: Reg, rs2: Reg },
18    Sh3add { rd: Reg, rs1: Reg, rs2: Reg },
19}
20
21#[instruction]
22const impl<Reg> Instruction for Rv32ZbaInstruction<Reg>
23where
24    Reg: [const] Register<Type = u32>,
25{
26    const ALIGNMENT: u8 = align_of::<u32>() as u8;
27
28    type Reg = Reg;
29
30    #[inline(always)]
31    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
32    fn try_decode(instruction: u32) -> Option<Self> {
33        let opcode = (instruction & 0b111_1111) as u8;
34        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
35        let funct3 = ((instruction >> 12) & 0b111) as u8;
36        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
37        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
38        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
39
40        match opcode {
41            // R-type
42            0b011_0011 => {
43                let rd = Reg::from_bits(rd_bits)?;
44                let rs1 = Reg::from_bits(rs1_bits)?;
45                let rs2 = Reg::from_bits(rs2_bits)?;
46                match (funct3, funct7) {
47                    (0b010, 0b001_0000) => Some(Self::Sh1add { rd, rs1, rs2 }),
48                    (0b100, 0b001_0000) => Some(Self::Sh2add { rd, rs1, rs2 }),
49                    (0b110, 0b001_0000) => Some(Self::Sh3add { rd, rs1, rs2 }),
50                    _ => None,
51                }
52            }
53            _ => None,
54        }
55    }
56
57    #[inline(always)]
58    fn size(&self) -> u8 {
59        size_of::<u32>() as u8
60    }
61}
62
63#[instruction]
64impl<Reg> fmt::Display for Rv32ZbaInstruction<Reg>
65where
66    Reg: fmt::Display,
67{
68    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
69        match self {
70            Self::Sh1add { rd, rs1, rs2 } => write!(f, "sh1add {rd}, {rs1}, {rs2}"),
71            Self::Sh2add { rd, rs1, rs2 } => write!(f, "sh2add {rd}, {rs1}, {rs2}"),
72            Self::Sh3add { rd, rs1, rs2 } => write!(f, "sh3add {rd}, {rs1}, {rs2}"),
73        }
74    }
75}
ab_riscv_primitives/instructions/rv32/b/zba.rs

ab_riscv_primitives/instructions/rv32/b/
zba.rs
