ab_riscv_primitives/instructions/rv32/
b.rs

1//! RV32 B extension
2
3pub mod zba;
4pub mod zbb;
5pub mod zbc;
6pub mod zbs;
7
8use crate::hart::HartConfig;
9use crate::instructions::rv32::b::zba::Rv32ZbaInstruction;
10use crate::instructions::rv32::b::zbb::{Rv32ZbbInstruction, Rv32ZbbZbkbSharedInstruction};
11use crate::instructions::rv32::b::zbs::Rv32ZbsInstruction;
12use crate::instructions::utils::Shamt;
13use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
14use crate::registers::general_purpose::Register;
15use ab_riscv_macros::instruction;
16use core::fmt;
17
18/// RISC-V RV32 B (Zba + Zbb + Zbs) instruction
19#[instruction(
20    inherit = [Rv32ZbaInstruction, Rv32ZbbInstruction, Rv32ZbsInstruction]
21)]
22#[derive(Debug, Clone, Copy)]
23#[derive_const(PartialEq, Eq)]
24pub enum Rv32BInstruction<Hart>
25where
26    Hart: HartConfig, {}
27
28#[instruction]
29const impl<Reg, Hart> Instruction for Rv32BInstruction<Hart>
30where
31    Reg: [const] Register<Type = u32>,
32    Hart: [const] HartConfig<Reg = Reg>,
33{
34    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("b", 1, 0)];
35
36    const ALIGNMENT: u8 = align_of::<u32>() as u8;
37
38    type Hart = Hart;
39
40    #[inline(always)]
41    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
42    fn try_decode(instruction: u32) -> Option<Self> {
43        None
44    }
45
46    #[inline(always)]
47    fn size(&self) -> u8 {
48        size_of::<u32>() as u8
49    }
50}
51
52#[instruction]
53impl<Reg, Hart> fmt::Display for Rv32BInstruction<Hart>
54where
55    Reg: fmt::Display + Copy,
56    Hart: HartConfig<Reg = Reg>,
57{
58    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
59        match self {}
60    }
61}
ab_riscv_primitives/instructions/rv32/b.rs

ab_riscv_primitives/instructions/rv32/
b.rs
