ab_riscv_primitives/instructions/rv32/
b.rs

1//! RV32 B extension
2
3pub mod zba;
4pub mod zbb;
5pub mod zbc;
6pub mod zbs;
7
8use crate::instructions::Instruction;
9use crate::instructions::rv32::b::zba::Rv32ZbaInstruction;
10use crate::instructions::rv32::b::zbb::Rv32ZbbInstruction;
11use crate::instructions::rv32::b::zbs::Rv32ZbsInstruction;
12use crate::registers::general_purpose::Register;
13use ab_riscv_macros::instruction;
14use core::fmt;
15
16/// RISC-V RV32 B (Zba + Zbb + Zbs) instruction
17#[instruction(
18    inherit = [Rv32ZbaInstruction, Rv32ZbbInstruction, Rv32ZbsInstruction]
19)]
20#[derive(Debug, Clone, Copy, PartialEq, Eq)]
21pub enum Rv32BInstruction<Reg> {}
22
23#[instruction]
24impl<Reg> const Instruction for Rv32BInstruction<Reg>
25where
26    Reg: [const] Register<Type = u32>,
27{
28    type Reg = Reg;
29
30    #[inline(always)]
31    fn try_decode(instruction: u32) -> Option<Self> {
32        None
33    }
34
35    #[inline(always)]
36    fn alignment() -> u8 {
37        size_of::<u32>() as u8
38    }
39
40    #[inline(always)]
41    fn size(&self) -> u8 {
42        size_of::<u32>() as u8
43    }
44}
45
46#[instruction]
47impl<Reg> fmt::Display for Rv32BInstruction<Reg>
48where
49    Reg: fmt::Display + Copy,
50{
51    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
52        match self {}
53    }
54}
ab_riscv_primitives/instructions/rv32/b.rs

ab_riscv_primitives/instructions/rv32/
b.rs
