ab_riscv_primitives/instructions/rv32/
b.rs

1//! RV32 B extension
2
3pub mod zba;
4pub mod zbb;
5pub mod zbc;
6pub mod zbs;
7
8use crate::instructions::Instruction;
9use crate::instructions::rv32::b::zba::Rv32ZbaInstruction;
10use crate::instructions::rv32::b::zbb::Rv32ZbbInstruction;
11use crate::instructions::rv32::b::zbs::Rv32ZbsInstruction;
12use crate::registers::general_purpose::Register;
13use ab_riscv_macros::instruction;
14use core::fmt;
15
16/// RISC-V RV32 B (Zba + Zbb + Zbs) instruction
17#[instruction(
18    inherit = [Rv32ZbaInstruction, Rv32ZbbInstruction, Rv32ZbsInstruction]
19)]
20#[derive(Debug, Clone, Copy)]
21#[derive_const(PartialEq, Eq)]
22pub enum Rv32BInstruction<Reg> {}
23
24#[instruction]
25const impl<Reg> Instruction for Rv32BInstruction<Reg>
26where
27    Reg: [const] Register<Type = u32>,
28{
29    type Reg = Reg;
30
31    #[inline(always)]
32    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
33    fn try_decode(instruction: u32) -> Option<Self> {
34        None
35    }
36
37    #[inline(always)]
38    fn alignment() -> u8 {
39        align_of::<u32>() as u8
40    }
41
42    #[inline(always)]
43    fn size(&self) -> u8 {
44        size_of::<u32>() as u8
45    }
46}
47
48#[instruction]
49impl<Reg> fmt::Display for Rv32BInstruction<Reg>
50where
51    Reg: fmt::Display + Copy,
52{
53    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
54        match self {}
55    }
56}
ab_riscv_primitives/instructions/rv32/b.rs

ab_riscv_primitives/instructions/rv32/
b.rs
