ab_riscv_primitives/instructions/rv32/a/
zalrsc.rs

1//! RV32 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zalrsc instruction (Load-Reserved/Store-Conditional)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15#[rustfmt::skip]
16pub enum Rv32ZalrscInstruction<Reg> {
17    Lr { rd: Reg, rs1: Reg, aq: bool, rl: bool },
18    Sc { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
19}
20
21#[instruction]
22const impl<Reg> Instruction for Rv32ZalrscInstruction<Reg>
23where
24    Reg: [const] Register<Type = u32>,
25{
26    type Reg = Reg;
27
28    #[inline(always)]
29    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
30    fn try_decode(instruction: u32) -> Option<Self> {
31        let opcode = (instruction & 0b111_1111) as u8;
32        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
33        let funct3 = ((instruction >> 12) & 0b111) as u8;
34        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
35        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
36        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
37
38        match (opcode, funct3) {
39            // AMO, word-sized (only size that exists in RV32)
40            (0b010_1111, 0b010) => {
41                let rd = Reg::from_bits(rd_bits)?;
42                let rs1 = Reg::from_bits(rs1_bits)?;
43                let funct5 = funct7 >> 2;
44                let aq = (funct7 & 0b10) != 0;
45                let rl = (funct7 & 0b01) != 0;
46
47                match (funct5, rs2_bits) {
48                    (0b00010, 0) => Some(Self::Lr { rd, rs1, aq, rl }),
49                    (0b00011, _) => {
50                        let rs2 = Reg::from_bits(rs2_bits)?;
51                        Some(Self::Sc {
52                            rd,
53                            rs1,
54                            rs2,
55                            aq,
56                            rl,
57                        })
58                    }
59                    _ => None,
60                }
61            }
62            _ => None,
63        }
64    }
65
66    #[inline(always)]
67    fn alignment() -> u8 {
68        align_of::<u32>() as u8
69    }
70
71    #[inline(always)]
72    fn size(&self) -> u8 {
73        size_of::<u32>() as u8
74    }
75}
76
77/// Format `aq`/`rl` suffix for display
78#[inline(always)]
79fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
80    match (*aq, *rl) {
81        (false, false) => "",
82        (true, false) => ".aq",
83        (false, true) => ".rl",
84        (true, true) => ".aqrl",
85    }
86}
87
88#[instruction]
89impl<Reg> fmt::Display for Rv32ZalrscInstruction<Reg>
90where
91    Reg: fmt::Display,
92{
93    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
94        #[rustfmt::skip]
95        match self {
96            Self::Lr { rd, rs1, aq, rl } => write!(f, "lr.w{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
97            Self::Sc { rd, rs1, rs2, aq, rl } => write!(f, "sc.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
98        }
99    }
100}
ab_riscv_primitives/instructions/rv32/a/zalrsc.rs

ab_riscv_primitives/instructions/rv32/a/
zalrsc.rs
