ab_riscv_primitives/instructions/rv32/a/
zalrsc.rs

1//! RV32 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instructions::Instruction;
7use crate::registers::general_purpose::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV32 Zalrsc instruction (Load-Reserved/Store-Conditional)
12#[instruction]
13#[derive(Debug, Clone, Copy)]
14#[derive_const(PartialEq, Eq)]
15#[rustfmt::skip]
16pub enum Rv32ZalrscInstruction<Reg> {
17    Lr { rd: Reg, rs1: Reg, aq: bool, rl: bool },
18    Sc { rd: Reg, rs1: Reg, rs2: Reg, aq: bool, rl: bool },
19}
20
21#[instruction]
22const impl<Reg> Instruction for Rv32ZalrscInstruction<Reg>
23where
24    Reg: [const] Register<Type = u32>,
25{
26    const ALIGNMENT: u8 = align_of::<u32>() as u8;
27
28    type Reg = Reg;
29
30    #[inline(always)]
31    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
32    fn try_decode(instruction: u32) -> Option<Self> {
33        let opcode = (instruction & 0b111_1111) as u8;
34        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
35        let funct3 = ((instruction >> 12) & 0b111) as u8;
36        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
37        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
38        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
39
40        match (opcode, funct3) {
41            // AMO, word-sized (only size that exists in RV32)
42            (0b010_1111, 0b010) => {
43                let rd = Reg::from_bits(rd_bits)?;
44                let rs1 = Reg::from_bits(rs1_bits)?;
45                let funct5 = funct7 >> 2;
46                let aq = (funct7 & 0b10) != 0;
47                let rl = (funct7 & 0b01) != 0;
48
49                match (funct5, rs2_bits) {
50                    (0b00010, 0) => Some(Self::Lr { rd, rs1, aq, rl }),
51                    (0b00011, _) => {
52                        let rs2 = Reg::from_bits(rs2_bits)?;
53                        Some(Self::Sc {
54                            rd,
55                            rs1,
56                            rs2,
57                            aq,
58                            rl,
59                        })
60                    }
61                    _ => None,
62                }
63            }
64            _ => None,
65        }
66    }
67
68    #[inline(always)]
69    fn size(&self) -> u8 {
70        size_of::<u32>() as u8
71    }
72}
73
74/// Format `aq`/`rl` suffix for display
75#[inline(always)]
76fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
77    match (*aq, *rl) {
78        (false, false) => "",
79        (true, false) => ".aq",
80        (false, true) => ".rl",
81        (true, true) => ".aqrl",
82    }
83}
84
85#[instruction]
86impl<Reg> fmt::Display for Rv32ZalrscInstruction<Reg>
87where
88    Reg: fmt::Display,
89{
90    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
91        #[rustfmt::skip]
92        match self {
93            Self::Lr { rd, rs1, aq, rl } => write!(f, "lr.w{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
94            Self::Sc { rd, rs1, rs2, aq, rl } => write!(f, "sc.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
95        }
96    }
97}
ab_riscv_primitives/instructions/rv32/a/zalrsc.rs

ab_riscv_primitives/instructions/rv32/a/
zalrsc.rs
