ab_riscv_primitives/instructions/rv32/a/
zalrsc.rs

1//! RV32 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::hart::HartConfig;
7use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
8use crate::registers::general_purpose::Register;
9use ab_riscv_macros::instruction;
10use core::fmt;
11
12/// RISC-V RV32 Zalrsc instruction (Load-Reserved/Store-Conditional)
13#[instruction]
14#[derive(Debug, Clone, Copy)]
15#[derive_const(PartialEq, Eq)]
16#[rustfmt::skip]
17pub enum Rv32ZalrscInstruction<Hart>
18where
19    Hart: HartConfig,
20{
21    Lr { rd: Hart::Reg, rs1: Hart::Reg, aq: bool, rl: bool },
22    Sc { rd: Hart::Reg, rs1: Hart::Reg, rs2: Hart::Reg, aq: bool, rl: bool },
23}
24
25#[instruction]
26const impl<Reg, Hart> Instruction for Rv32ZalrscInstruction<Hart>
27where
28    Reg: [const] Register<Type = u32>,
29    Hart: [const] HartConfig<Reg = Reg>,
30{
31    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("zalrsc", 1, 0)];
32
33    const ALIGNMENT: u8 = align_of::<u32>() as u8;
34
35    type Hart = Hart;
36
37    #[inline(always)]
38    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
39    fn try_decode(instruction: u32) -> Option<Self> {
40        let opcode = (instruction & 0b111_1111) as u8;
41        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
42        let funct3 = ((instruction >> 12) & 0b111) as u8;
43        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
44        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
45        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
46
47        match (opcode, funct3) {
48            // AMO, word-sized (only size that exists in RV32)
49            (0b010_1111, 0b010) => {
50                let rd = Reg::from_bits(rd_bits)?;
51                let rs1 = Reg::from_bits(rs1_bits)?;
52                let funct5 = funct7 >> 2;
53                let aq = (funct7 & 0b10) != 0;
54                let rl = (funct7 & 0b01) != 0;
55
56                match (funct5, rs2_bits) {
57                    (0b00010, 0) => Some(Self::Lr { rd, rs1, aq, rl }),
58                    (0b00011, _) => {
59                        let rs2 = Reg::from_bits(rs2_bits)?;
60                        Some(Self::Sc {
61                            rd,
62                            rs1,
63                            rs2,
64                            aq,
65                            rl,
66                        })
67                    }
68                    _ => None,
69                }
70            }
71            _ => None,
72        }
73    }
74
75    #[inline(always)]
76    fn size(&self) -> u8 {
77        size_of::<u32>() as u8
78    }
79}
80
81/// Format `aq`/`rl` suffix for display
82#[inline(always)]
83fn aq_rl_suffix(aq: &bool, rl: &bool) -> &'static str {
84    match (*aq, *rl) {
85        (false, false) => "",
86        (true, false) => ".aq",
87        (false, true) => ".rl",
88        (true, true) => ".aqrl",
89    }
90}
91
92#[instruction]
93impl<Reg, Hart> fmt::Display for Rv32ZalrscInstruction<Hart>
94where
95    Reg: fmt::Display,
96    Hart: HartConfig<Reg = Reg>,
97{
98    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
99        #[rustfmt::skip]
100        match self {
101            Self::Lr { rd, rs1, aq, rl } => write!(f, "lr.w{} {rd}, ({rs1})", aq_rl_suffix(aq, rl)),
102            Self::Sc { rd, rs1, rs2, aq, rl } => write!(f, "sc.w{} {rd}, {rs2}, ({rs1})", aq_rl_suffix(aq, rl)),
103        }
104    }
105}
ab_riscv_primitives/instructions/rv32/a/zalrsc.rs

ab_riscv_primitives/instructions/rv32/a/
zalrsc.rs
