ab_riscv_primitives/instructions/rv32/
a.rs

1//! RV32 A extension
2
3pub mod zaamo;
4pub mod zalrsc;
5
6use crate::hart::HartConfig;
7use crate::instructions::rv32::a::zaamo::Rv32ZaamoInstruction;
8use crate::instructions::rv32::a::zalrsc::Rv32ZalrscInstruction;
9use crate::instructions::{ImplementedExtension, Instruction, IsaExtension};
10use crate::registers::general_purpose::Register;
11use ab_riscv_macros::instruction;
12use core::fmt;
13
14/// RISC-V RV32 A (Zaamo + Zalrsc) instruction
15#[instruction(
16    inherit = [Rv32ZaamoInstruction, Rv32ZalrscInstruction]
17)]
18#[derive(Debug, Clone, Copy)]
19#[derive_const(PartialEq, Eq)]
20pub enum Rv32AInstruction<Hart>
21where
22    Hart: HartConfig, {}
23
24#[instruction]
25const impl<Reg, Hart> Instruction for Rv32AInstruction<Hart>
26where
27    Reg: [const] Register<Type = u32>,
28    Hart: [const] HartConfig<Reg = Reg>,
29{
30    const OWN_ISA_EXTENSIONS: &'static [IsaExtension] = &[IsaExtension::new("a", 2, 1)];
31
32    const ALIGNMENT: u8 = align_of::<u32>() as u8;
33
34    type Hart = Hart;
35
36    #[inline(always)]
37    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
38    fn try_decode(instruction: u32) -> Option<Self> {
39        None
40    }
41
42    #[inline(always)]
43    fn size(&self) -> u8 {
44        size_of::<u32>() as u8
45    }
46}
47
48#[instruction]
49impl<Reg, Hart> fmt::Display for Rv32AInstruction<Hart>
50where
51    Reg: fmt::Display + Copy,
52    Hart: HartConfig<Reg = Reg>,
53{
54    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
55        match self {}
56    }
57}
ab_riscv_primitives/instructions/rv32/a.rs

ab_riscv_primitives/instructions/rv32/
a.rs
