ab_riscv_primitives/instructions/
rv32.rs

1//! Base RISC-V RV32 instruction set
2
3pub mod b;
4pub mod c;
5pub mod m;
6#[cfg(test)]
7mod tests;
8pub mod zce;
9pub mod zk;
10
11use crate::instructions::Instruction;
12use crate::registers::general_purpose::Register;
13use ab_riscv_macros::instruction;
14use core::fmt;
15
16/// RISC-V RV32 instruction
17#[instruction]
18#[derive(Debug, Clone, Copy, PartialEq, Eq)]
19pub enum Rv32Instruction<Reg> {
20    // R-type
21    Add { rd: Reg, rs1: Reg, rs2: Reg },
22    Sub { rd: Reg, rs1: Reg, rs2: Reg },
23    Sll { rd: Reg, rs1: Reg, rs2: Reg },
24    Slt { rd: Reg, rs1: Reg, rs2: Reg },
25    Sltu { rd: Reg, rs1: Reg, rs2: Reg },
26    Xor { rd: Reg, rs1: Reg, rs2: Reg },
27    Srl { rd: Reg, rs1: Reg, rs2: Reg },
28    Sra { rd: Reg, rs1: Reg, rs2: Reg },
29    Or { rd: Reg, rs1: Reg, rs2: Reg },
30    And { rd: Reg, rs1: Reg, rs2: Reg },
31
32    // I-type
33    Addi { rd: Reg, rs1: Reg, imm: i16 },
34    Slti { rd: Reg, rs1: Reg, imm: i16 },
35    Sltiu { rd: Reg, rs1: Reg, imm: i16 },
36    Xori { rd: Reg, rs1: Reg, imm: i16 },
37    Ori { rd: Reg, rs1: Reg, imm: i16 },
38    Andi { rd: Reg, rs1: Reg, imm: i16 },
39    Slli { rd: Reg, rs1: Reg, shamt: u8 },
40    Srli { rd: Reg, rs1: Reg, shamt: u8 },
41    Srai { rd: Reg, rs1: Reg, shamt: u8 },
42
43    // Loads (I-type)
44    Lb { rd: Reg, rs1: Reg, imm: i16 },
45    Lh { rd: Reg, rs1: Reg, imm: i16 },
46    Lw { rd: Reg, rs1: Reg, imm: i16 },
47    Lbu { rd: Reg, rs1: Reg, imm: i16 },
48    Lhu { rd: Reg, rs1: Reg, imm: i16 },
49
50    // Jalr (I-type)
51    Jalr { rd: Reg, rs1: Reg, imm: i16 },
52
53    // S-type
54    Sb { rs2: Reg, rs1: Reg, imm: i16 },
55    Sh { rs2: Reg, rs1: Reg, imm: i16 },
56    Sw { rs2: Reg, rs1: Reg, imm: i16 },
57
58    // B-type
59    Beq { rs1: Reg, rs2: Reg, imm: i32 },
60    Bne { rs1: Reg, rs2: Reg, imm: i32 },
61    Blt { rs1: Reg, rs2: Reg, imm: i32 },
62    Bge { rs1: Reg, rs2: Reg, imm: i32 },
63    Bltu { rs1: Reg, rs2: Reg, imm: i32 },
64    Bgeu { rs1: Reg, rs2: Reg, imm: i32 },
65
66    // Lui (U-type)
67    Lui { rd: Reg, imm: i32 },
68
69    // Auipc (U-type)
70    Auipc { rd: Reg, imm: i32 },
71
72    // Jal (J-type)
73    Jal { rd: Reg, imm: i32 },
74
75    // Fence
76    Fence { pred: u8, succ: u8 },
77    FenceTso,
78
79    // System instructions
80    Ecall,
81    Ebreak,
82
83    // Unimplemented/illegal
84    Unimp,
85}
86
87#[instruction]
88impl<Reg> const Instruction for Rv32Instruction<Reg>
89where
90    Reg: [const] Register<Type = u32>,
91{
92    type Reg = Reg;
93
94    #[inline(always)]
95    fn try_decode(instruction: u32) -> Option<Self> {
96        let opcode = (instruction & 0b111_1111) as u8;
97        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
98        let funct3 = ((instruction >> 12) & 0b111) as u8;
99        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
100        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
101        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
102
103        match opcode {
104            // R-type
105            0b0110011 => {
106                let rd = Reg::from_bits(rd_bits)?;
107                let rs1 = Reg::from_bits(rs1_bits)?;
108                let rs2 = Reg::from_bits(rs2_bits)?;
109                match (funct3, funct7) {
110                    (0b000, 0b0000000) => Some(Self::Add { rd, rs1, rs2 }),
111                    (0b000, 0b0100000) => Some(Self::Sub { rd, rs1, rs2 }),
112                    (0b001, 0b0000000) => Some(Self::Sll { rd, rs1, rs2 }),
113                    (0b010, 0b0000000) => Some(Self::Slt { rd, rs1, rs2 }),
114                    (0b011, 0b0000000) => Some(Self::Sltu { rd, rs1, rs2 }),
115                    (0b100, 0b0000000) => Some(Self::Xor { rd, rs1, rs2 }),
116                    (0b101, 0b0000000) => Some(Self::Srl { rd, rs1, rs2 }),
117                    (0b101, 0b0100000) => Some(Self::Sra { rd, rs1, rs2 }),
118                    (0b110, 0b0000000) => Some(Self::Or { rd, rs1, rs2 }),
119                    (0b111, 0b0000000) => Some(Self::And { rd, rs1, rs2 }),
120                    _ => None,
121                }
122            }
123            // I-type
124            0b0010011 => {
125                let rd = Reg::from_bits(rd_bits)?;
126                let rs1 = Reg::from_bits(rs1_bits)?;
127                let imm = (instruction.cast_signed() >> 20) as i16;
128                match funct3 {
129                    0b000 => Some(Self::Addi { rd, rs1, imm }),
130                    0b010 => Some(Self::Slti { rd, rs1, imm }),
131                    0b011 => Some(Self::Sltiu { rd, rs1, imm }),
132                    0b100 => Some(Self::Xori { rd, rs1, imm }),
133                    0b110 => Some(Self::Ori { rd, rs1, imm }),
134                    0b111 => Some(Self::Andi { rd, rs1, imm }),
135                    0b001 => {
136                        // RV32: 5-bit shamt, funct7 must be 0b0000000
137                        let shamt = (instruction >> 20) as u8 & 0b1_1111;
138                        if funct7 == 0b0000000 {
139                            Some(Self::Slli { rd, rs1, shamt })
140                        } else {
141                            None
142                        }
143                    }
144                    0b101 => {
145                        // RV32: 5-bit shamt, funct7 distinguishes SRLI/SRAI
146                        let shamt = (instruction >> 20) as u8 & 0b1_1111;
147                        match funct7 {
148                            0b0000000 => Some(Self::Srli { rd, rs1, shamt }),
149                            0b0100000 => Some(Self::Srai { rd, rs1, shamt }),
150                            _ => None,
151                        }
152                    }
153                    _ => None,
154                }
155            }
156            // Loads (I-type)
157            0b0000011 => {
158                let rd = Reg::from_bits(rd_bits)?;
159                let rs1 = Reg::from_bits(rs1_bits)?;
160                let imm = (instruction.cast_signed() >> 20) as i16;
161                match funct3 {
162                    0b000 => Some(Self::Lb { rd, rs1, imm }),
163                    0b001 => Some(Self::Lh { rd, rs1, imm }),
164                    0b010 => Some(Self::Lw { rd, rs1, imm }),
165                    0b100 => Some(Self::Lbu { rd, rs1, imm }),
166                    0b101 => Some(Self::Lhu { rd, rs1, imm }),
167                    _ => None,
168                }
169            }
170            // Jalr (I-type)
171            0b1100111 => {
172                let rd = Reg::from_bits(rd_bits)?;
173                let rs1 = Reg::from_bits(rs1_bits)?;
174                if funct3 == 0b000 {
175                    let imm = (instruction.cast_signed() >> 20) as i16;
176                    Some(Self::Jalr { rd, rs1, imm })
177                } else {
178                    None
179                }
180            }
181            // S-type
182            0b0100011 => {
183                let rs1 = Reg::from_bits(rs1_bits)?;
184                let rs2 = Reg::from_bits(rs2_bits)?;
185                let imm11_5 = ((instruction >> 25) & 0b111_1111).cast_signed();
186                let imm4_0 = ((instruction >> 7) & 0b1_1111).cast_signed();
187                let imm = (imm11_5 << 5) | imm4_0;
188                // Sign extend
189                let imm = ((imm << 20) >> 20) as i16;
190                match funct3 {
191                    0b000 => Some(Self::Sb { rs2, rs1, imm }),
192                    0b001 => Some(Self::Sh { rs2, rs1, imm }),
193                    0b010 => Some(Self::Sw { rs2, rs1, imm }),
194                    _ => None,
195                }
196            }
197            // B-type
198            0b1100011 => {
199                let rs1 = Reg::from_bits(rs1_bits)?;
200                let rs2 = Reg::from_bits(rs2_bits)?;
201                let imm12 = ((instruction >> 31) & 1).cast_signed();
202                let imm10_5 = ((instruction >> 25) & 0b11_1111).cast_signed();
203                let imm4_1 = ((instruction >> 8) & 0b1111).cast_signed();
204                let imm11 = ((instruction >> 7) & 1).cast_signed();
205                let imm = (imm12 << 12) | (imm11 << 11) | (imm10_5 << 5) | (imm4_1 << 1);
206                // Sign extend
207                let imm = (imm << 19) >> 19;
208                match funct3 {
209                    0b000 => Some(Self::Beq { rs1, rs2, imm }),
210                    0b001 => Some(Self::Bne { rs1, rs2, imm }),
211                    0b100 => Some(Self::Blt { rs1, rs2, imm }),
212                    0b101 => Some(Self::Bge { rs1, rs2, imm }),
213                    0b110 => Some(Self::Bltu { rs1, rs2, imm }),
214                    0b111 => Some(Self::Bgeu { rs1, rs2, imm }),
215                    _ => None,
216                }
217            }
218            // Lui (U-type)
219            0b0110111 => {
220                let rd = Reg::from_bits(rd_bits)?;
221                let imm = (instruction & 0xffff_f000).cast_signed();
222                Some(Self::Lui { rd, imm })
223            }
224            // Auipc (U-type)
225            0b0010111 => {
226                let rd = Reg::from_bits(rd_bits)?;
227                let imm = (instruction & 0xffff_f000).cast_signed();
228                Some(Self::Auipc { rd, imm })
229            }
230            // Jal (J-type)
231            0b1101111 => {
232                let rd = Reg::from_bits(rd_bits)?;
233                let imm20 = ((instruction >> 31) & 1).cast_signed();
234                let imm10_1 = ((instruction >> 21) & 0b11_1111_1111).cast_signed();
235                let imm11 = ((instruction >> 20) & 1).cast_signed();
236                let imm19_12 = ((instruction >> 12) & 0b1111_1111).cast_signed();
237                let imm = (imm20 << 20) | (imm19_12 << 12) | (imm11 << 11) | (imm10_1 << 1);
238                // Sign extend
239                let imm = (imm << 11) >> 11;
240                Some(Self::Jal { rd, imm })
241            }
242            // Fence (I-type like, simplified for EM)
243            0b0001111 => {
244                if funct3 == 0b000 && rd_bits == 0 && rs1_bits == 0 {
245                    let fm = (instruction >> 28) & 0b1111;
246                    let pred = ((instruction >> 24) & 0xf) as u8;
247                    let succ = ((instruction >> 20) & 0xf) as u8;
248                    match fm {
249                        0b0000 => Some(Self::Fence { pred, succ }),
250                        0b1000 => {
251                            // FENCE.TSO: fm=8, pred=RW(0b0011), succ=RW(0b0011) - fixed by spec
252                            if pred == 0b0011 && succ == 0b0011 {
253                                Some(Self::FenceTso)
254                            } else {
255                                None
256                            }
257                        }
258                        _ => None,
259                    }
260                } else {
261                    None
262                }
263            }
264            // System instructions
265            0b1110011 => {
266                let imm = (instruction >> 20) & 0xfff;
267                if funct3 == 0 && rd_bits == 0 && rs1_bits == 0 {
268                    match imm {
269                        0 => Some(Self::Ecall),
270                        1 => Some(Self::Ebreak),
271                        _ => None,
272                    }
273                } else if funct3 == 0b001 && rd_bits == 0 && rs1_bits == 0 && imm == 0xc00 {
274                    // `0xc0001073` is emitted as `unimp`/illegal instruction by various compilers,
275                    // including Rust when it hits a panic
276                    Some(Self::Unimp)
277                } else {
278                    None
279                }
280            }
281            _ => None,
282        }
283    }
284
285    #[inline(always)]
286    fn alignment() -> u8 {
287        align_of::<u32>() as u8
288    }
289
290    #[inline(always)]
291    fn size(&self) -> u8 {
292        size_of::<u32>() as u8
293    }
294}
295
296impl<Reg> fmt::Display for Rv32Instruction<Reg>
297where
298    Reg: fmt::Display,
299{
300    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
301        match self {
302            Self::Add { rd, rs1, rs2 } => write!(f, "add {}, {}, {}", rd, rs1, rs2),
303            Self::Sub { rd, rs1, rs2 } => write!(f, "sub {}, {}, {}", rd, rs1, rs2),
304            Self::Sll { rd, rs1, rs2 } => write!(f, "sll {}, {}, {}", rd, rs1, rs2),
305            Self::Slt { rd, rs1, rs2 } => write!(f, "slt {}, {}, {}", rd, rs1, rs2),
306            Self::Sltu { rd, rs1, rs2 } => write!(f, "sltu {}, {}, {}", rd, rs1, rs2),
307            Self::Xor { rd, rs1, rs2 } => write!(f, "xor {}, {}, {}", rd, rs1, rs2),
308            Self::Srl { rd, rs1, rs2 } => write!(f, "srl {}, {}, {}", rd, rs1, rs2),
309            Self::Sra { rd, rs1, rs2 } => write!(f, "sra {}, {}, {}", rd, rs1, rs2),
310            Self::Or { rd, rs1, rs2 } => write!(f, "or {}, {}, {}", rd, rs1, rs2),
311            Self::And { rd, rs1, rs2 } => write!(f, "and {}, {}, {}", rd, rs1, rs2),
312
313            Self::Addi { rd, rs1, imm } => write!(f, "addi {}, {}, {}", rd, rs1, imm),
314            Self::Slti { rd, rs1, imm } => write!(f, "slti {}, {}, {}", rd, rs1, imm),
315            Self::Sltiu { rd, rs1, imm } => write!(f, "sltiu {}, {}, {}", rd, rs1, imm),
316            Self::Xori { rd, rs1, imm } => write!(f, "xori {}, {}, {}", rd, rs1, imm),
317            Self::Ori { rd, rs1, imm } => write!(f, "ori {}, {}, {}", rd, rs1, imm),
318            Self::Andi { rd, rs1, imm } => write!(f, "andi {}, {}, {}", rd, rs1, imm),
319            Self::Slli { rd, rs1, shamt } => write!(f, "slli {}, {}, {}", rd, rs1, shamt),
320            Self::Srli { rd, rs1, shamt } => write!(f, "srli {}, {}, {}", rd, rs1, shamt),
321            Self::Srai { rd, rs1, shamt } => write!(f, "srai {}, {}, {}", rd, rs1, shamt),
322
323            Self::Lb { rd, rs1, imm } => write!(f, "lb {}, {}({})", rd, imm, rs1),
324            Self::Lh { rd, rs1, imm } => write!(f, "lh {}, {}({})", rd, imm, rs1),
325            Self::Lw { rd, rs1, imm } => write!(f, "lw {}, {}({})", rd, imm, rs1),
326            Self::Lbu { rd, rs1, imm } => write!(f, "lbu {}, {}({})", rd, imm, rs1),
327            Self::Lhu { rd, rs1, imm } => write!(f, "lhu {}, {}({})", rd, imm, rs1),
328
329            Self::Jalr { rd, rs1, imm } => write!(f, "jalr {}, {}({})", rd, imm, rs1),
330
331            Self::Sb { rs2, rs1, imm } => write!(f, "sb {}, {}({})", rs2, imm, rs1),
332            Self::Sh { rs2, rs1, imm } => write!(f, "sh {}, {}({})", rs2, imm, rs1),
333            Self::Sw { rs2, rs1, imm } => write!(f, "sw {}, {}({})", rs2, imm, rs1),
334
335            Self::Beq { rs1, rs2, imm } => write!(f, "beq {}, {}, {}", rs1, rs2, imm),
336            Self::Bne { rs1, rs2, imm } => write!(f, "bne {}, {}, {}", rs1, rs2, imm),
337            Self::Blt { rs1, rs2, imm } => write!(f, "blt {}, {}, {}", rs1, rs2, imm),
338            Self::Bge { rs1, rs2, imm } => write!(f, "bge {}, {}, {}", rs1, rs2, imm),
339            Self::Bltu { rs1, rs2, imm } => write!(f, "bltu {}, {}, {}", rs1, rs2, imm),
340            Self::Bgeu { rs1, rs2, imm } => write!(f, "bgeu {}, {}, {}", rs1, rs2, imm),
341
342            Self::Lui { rd, imm } => write!(f, "lui {}, 0x{:x}", rd, imm >> 12),
343
344            Self::Auipc { rd, imm } => write!(f, "auipc {}, 0x{:x}", rd, imm >> 12),
345
346            Self::Jal { rd, imm } => write!(f, "jal {}, {}", rd, imm),
347
348            Self::Fence { pred, succ } => write!(f, "fence {}, {}", pred, succ),
349            Self::FenceTso => write!(f, "fence.tso"),
350
351            Self::Ecall => write!(f, "ecall"),
352            Self::Ebreak => write!(f, "ebreak"),
353
354            Self::Unimp => write!(f, "unimp"),
355        }
356    }
357}
ab_riscv_primitives/instructions/rv32.rs

ab_riscv_primitives/instructions/
rv32.rs
