ab_riscv_primitives/instruction/rv64/zk/zkn/
zknh.rs

1//! RV64 Zknh extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instruction::Instruction;
7use crate::registers::Register;
8use ab_riscv_macros::instruction;
9use core::fmt;
10
11/// RISC-V RV64 Zknh instruction (SHA-256 and SHA-512 sigma functions)
12#[instruction]
13#[derive(Debug, Clone, Copy, PartialEq, Eq)]
14pub enum Rv64ZknhInstruction<Reg> {
15    Sha256Sig0 { rd: Reg, rs1: Reg },
16    Sha256Sig1 { rd: Reg, rs1: Reg },
17    Sha256Sum0 { rd: Reg, rs1: Reg },
18    Sha256Sum1 { rd: Reg, rs1: Reg },
19    Sha512Sig0 { rd: Reg, rs1: Reg },
20    Sha512Sig1 { rd: Reg, rs1: Reg },
21    Sha512Sum0 { rd: Reg, rs1: Reg },
22    Sha512Sum1 { rd: Reg, rs1: Reg },
23}
24
25#[instruction]
26impl<Reg> const Instruction for Rv64ZknhInstruction<Reg>
27where
28    Reg: [const] Register<Type = u64>,
29{
30    type Reg = Reg;
31
32    #[inline(always)]
33    fn try_decode(instruction: u32) -> Option<Self> {
34        let opcode = (instruction & 0b111_1111) as u8;
35        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
36        let funct3 = ((instruction >> 12) & 0b111) as u8;
37        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
38        let funct5 = ((instruction >> 20) & 0x1f) as u8;
39        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
40
41        match opcode {
42            // I-type format (OP-IMM encoding)
43            0b0010011 => {
44                if funct3 != 0b001 || funct7 != 0b0001000 {
45                    None
46                } else {
47                    let rd = Reg::from_bits(rd_bits)?;
48                    let rs1 = Reg::from_bits(rs1_bits)?;
49                    match funct5 {
50                        // SHA-256 instructions
51                        0b00010 => Some(Self::Sha256Sig0 { rd, rs1 }),
52                        0b00011 => Some(Self::Sha256Sig1 { rd, rs1 }),
53                        0b00000 => Some(Self::Sha256Sum0 { rd, rs1 }),
54                        0b00001 => Some(Self::Sha256Sum1 { rd, rs1 }),
55                        // SHA-512 instructions
56                        0b00110 => Some(Self::Sha512Sig0 { rd, rs1 }),
57                        0b00111 => Some(Self::Sha512Sig1 { rd, rs1 }),
58                        0b00100 => Some(Self::Sha512Sum0 { rd, rs1 }),
59                        0b00101 => Some(Self::Sha512Sum1 { rd, rs1 }),
60                        _ => None,
61                    }
62                }
63            }
64            _ => None,
65        }
66    }
67
68    #[inline(always)]
69    fn alignment() -> u8 {
70        size_of::<u32>() as u8
71    }
72
73    #[inline(always)]
74    fn size(&self) -> u8 {
75        size_of::<u32>() as u8
76    }
77}
78
79impl<Reg> fmt::Display for Rv64ZknhInstruction<Reg>
80where
81    Reg: fmt::Display,
82{
83    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
84        match self {
85            Self::Sha256Sig0 { rd, rs1 } => write!(f, "sha256sig0 {}, {}", rd, rs1),
86            Self::Sha256Sig1 { rd, rs1 } => write!(f, "sha256sig1 {}, {}", rd, rs1),
87            Self::Sha256Sum0 { rd, rs1 } => write!(f, "sha256sum0 {}, {}", rd, rs1),
88            Self::Sha256Sum1 { rd, rs1 } => write!(f, "sha256sum1 {}, {}", rd, rs1),
89            Self::Sha512Sig0 { rd, rs1 } => write!(f, "sha512sig0 {}, {}", rd, rs1),
90            Self::Sha512Sig1 { rd, rs1 } => write!(f, "sha512sig1 {}, {}", rd, rs1),
91            Self::Sha512Sum0 { rd, rs1 } => write!(f, "sha512sum0 {}, {}", rd, rs1),
92            Self::Sha512Sum1 { rd, rs1 } => write!(f, "sha512sum1 {}, {}", rd, rs1),
93        }
94    }
95}
ab_riscv_primitives/instruction/rv64/zk/zkn/zknh.rs

ab_riscv_primitives/instruction/rv64/zk/zkn/
zknh.rs
