ab_riscv_primitives/instruction/rv64/b/
zbs.rs

1//! RV64 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::instruction::Instruction;
7use crate::instruction::rv64::Rv64Instruction;
8use crate::registers::Register;
9use core::fmt;
10
11/// RISC-V RV64 Zbs instruction (Single-bit instructions)
12#[derive(Debug, Clone, Copy, PartialEq, Eq)]
13pub enum Rv64ZbsInstruction<Reg> {
14    // Single-Bit Set
15    Bset { rd: Reg, rs1: Reg, rs2: Reg },
16    Bseti { rd: Reg, rs1: Reg, shamt: u8 },
17
18    // Single-Bit Clear
19    Bclr { rd: Reg, rs1: Reg, rs2: Reg },
20    Bclri { rd: Reg, rs1: Reg, shamt: u8 },
21
22    // Single-Bit Invert
23    Binv { rd: Reg, rs1: Reg, rs2: Reg },
24    Binvi { rd: Reg, rs1: Reg, shamt: u8 },
25
26    // Single-Bit Extract
27    Bext { rd: Reg, rs1: Reg, rs2: Reg },
28    Bexti { rd: Reg, rs1: Reg, shamt: u8 },
29}
30
31impl<Reg> const Instruction for Rv64ZbsInstruction<Reg>
32where
33    Reg: [const] Register<Type = u64>,
34{
35    type Base = Rv64Instruction<Reg>;
36
37    #[inline(always)]
38    fn try_decode(instruction: u32) -> Option<Self> {
39        let opcode = (instruction & 0b111_1111) as u8;
40        let rd_bits = ((instruction >> 7) & 0x1f) as u8;
41        let funct3 = ((instruction >> 12) & 0b111) as u8;
42        let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
43        let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
44        let shamt = ((instruction >> 20) & 0x3f) as u8;
45        let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
46        let funct6 = ((instruction >> 26) & 0b11_1111) as u8;
47
48        Some(match opcode {
49            // R-type instructions
50            0b0110011 => {
51                let rd = Reg::from_bits(rd_bits)?;
52                let rs1 = Reg::from_bits(rs1_bits)?;
53                let rs2 = Reg::from_bits(rs2_bits)?;
54                match (funct3, funct7) {
55                    (0b001, 0b0010100) => Self::Bset { rd, rs1, rs2 },
56                    (0b001, 0b0100100) => Self::Bclr { rd, rs1, rs2 },
57                    (0b001, 0b0110100) => Self::Binv { rd, rs1, rs2 },
58                    (0b101, 0b0100100) => Self::Bext { rd, rs1, rs2 },
59                    _ => {
60                        return None;
61                    }
62                }
63            }
64            // I-type instructions
65            0b0010011 => {
66                let rd = Reg::from_bits(rd_bits)?;
67                let rs1 = Reg::from_bits(rs1_bits)?;
68                match (funct3, funct6) {
69                    (0b001, 0b001010) => Self::Bseti { rd, rs1, shamt },
70                    (0b001, 0b010010) => Self::Bclri { rd, rs1, shamt },
71                    (0b001, 0b011010) => Self::Binvi { rd, rs1, shamt },
72                    (0b101, 0b010010) => Self::Bexti { rd, rs1, shamt },
73                    _ => {
74                        return None;
75                    }
76                }
77            }
78            _ => {
79                return None;
80            }
81        })
82    }
83
84    #[inline(always)]
85    fn size(&self) -> u8 {
86        size_of::<u32>() as u8
87    }
88}
89
90impl<Reg> fmt::Display for Rv64ZbsInstruction<Reg>
91where
92    Reg: fmt::Display,
93{
94    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
95        match self {
96            Self::Bset { rd, rs1, rs2 } => write!(f, "bset {}, {}, {}", rd, rs1, rs2),
97            Self::Bseti { rd, rs1, shamt } => write!(f, "bseti {}, {}, {}", rd, rs1, shamt),
98            Self::Bclr { rd, rs1, rs2 } => write!(f, "bclr {}, {}, {}", rd, rs1, rs2),
99            Self::Bclri { rd, rs1, shamt } => write!(f, "bclri {}, {}, {}", rd, rs1, shamt),
100            Self::Binv { rd, rs1, rs2 } => write!(f, "binv {}, {}, {}", rd, rs1, rs2),
101            Self::Binvi { rd, rs1, shamt } => write!(f, "binvi {}, {}, {}", rd, rs1, shamt),
102            Self::Bext { rd, rs1, rs2 } => write!(f, "bext {}, {}, {}", rd, rs1, rs2),
103            Self::Bexti { rd, rs1, shamt } => write!(f, "bexti {}, {}, {}", rd, rs1, shamt),
104        }
105    }
106}
ab_riscv_primitives/instruction/rv64/b/zbs.rs

ab_riscv_primitives/instruction/rv64/b/
zbs.rs
