ab_riscv_primitives/instruction/rv64/b/
zbc.rs1#[cfg(test)]
4mod tests;
5
6use crate::instruction::Instruction;
7use crate::instruction::rv64::Rv64Instruction;
8use crate::registers::Register;
9use core::fmt;
10
11#[derive(Debug, Clone, Copy, PartialEq, Eq)]
13pub enum Rv64ZbcInstruction<Reg> {
14 Clmul { rd: Reg, rs1: Reg, rs2: Reg },
15 Clmulh { rd: Reg, rs1: Reg, rs2: Reg },
16 Clmulr { rd: Reg, rs1: Reg, rs2: Reg },
17}
18
19impl<Reg> const Instruction for Rv64ZbcInstruction<Reg>
20where
21 Reg: [const] Register<Type = u64>,
22{
23 type Base = Rv64Instruction<Reg>;
24
25 #[inline(always)]
26 fn try_decode(instruction: u32) -> Option<Self> {
27 let opcode = (instruction & 0b111_1111) as u8;
28 let rd_bits = ((instruction >> 7) & 0x1f) as u8;
29 let funct3 = ((instruction >> 12) & 0b111) as u8;
30 let rs1_bits = ((instruction >> 15) & 0x1f) as u8;
31 let rs2_bits = ((instruction >> 20) & 0x1f) as u8;
32 let funct7 = ((instruction >> 25) & 0b111_1111) as u8;
33
34 Some(match opcode {
35 0b0110011 => {
37 let rd = Reg::from_bits(rd_bits)?;
38 let rs1 = Reg::from_bits(rs1_bits)?;
39 let rs2 = Reg::from_bits(rs2_bits)?;
40 match (funct3, funct7) {
41 (0b001, 0b0000101) => Self::Clmul { rd, rs1, rs2 },
42 (0b011, 0b0000101) => Self::Clmulh { rd, rs1, rs2 },
43 (0b010, 0b0000101) => Self::Clmulr { rd, rs1, rs2 },
44 _ => {
45 return None;
46 }
47 }
48 }
49 _ => {
50 return None;
51 }
52 })
53 }
54
55 #[inline(always)]
56 fn size(&self) -> u8 {
57 size_of::<u32>() as u8
58 }
59}
60
61impl<Reg> fmt::Display for Rv64ZbcInstruction<Reg>
62where
63 Reg: fmt::Display,
64{
65 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
66 match self {
67 Self::Clmul { rd, rs1, rs2 } => write!(f, "clmul {}, {}, {}", rd, rs1, rs2),
68 Self::Clmulh { rd, rs1, rs2 } => write!(f, "clmulh {}, {}, {}", rd, rs1, rs2),
69 Self::Clmulr { rd, rs1, rs2 } => write!(f, "clmulr {}, {}, {}", rd, rs1, rs2),
70 }
71 }
72}