ab_riscv_interpreter/v/zvexx/

mask.rs

//! ZveXx mask instructions

#[cfg(test)]
mod tests;
pub mod zvexx_mask_helpers;

use crate::v::vector_registers::VectorRegistersExt;
use crate::v::zvexx::zvexx_helpers;
use crate::{
    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
    ProgramCounter, RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, VirtualMemory,
};
use ab_riscv_macros::instruction_execution;
use ab_riscv_primitives::prelude::*;
use core::fmt;
use core::ops::ControlFlow;

#[instruction_execution]
impl<Reg> ExecutableInstructionOperands for ZveXxMaskInstruction<Reg> where Reg: Register {}

#[instruction_execution]
impl<Reg, ExtState, CustomError> ExecutableInstructionCsr<ExtState, CustomError>
    for ZveXxMaskInstruction<Reg>
where
    Reg: Register,
{
}

#[instruction_execution]
impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
    for ZveXxMaskInstruction<Reg>
where
    Reg: Register,
    Regs: RegisterFile<Reg>,
    ExtState: VectorRegistersExt<Reg, CustomError>,
    [(); ExtState::ELEN as usize]:,
    [(); ExtState::VLEN as usize]:,
    [(); ExtState::VLENB as usize]:,
    Memory: VirtualMemory,
    PC: ProgramCounter<Reg::Type, Memory, CustomError>,
    CustomError: fmt::Debug,
{
    #[inline(always)]
    fn execute(
        self,
        Rs1Rs2OperandValues {
            rs1_value: _,
            rs2_value: _,
        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
        regs: &mut Regs,
        ext_state: &mut ExtState,
        _memory: &mut Memory,
        program_counter: &mut PC,
        _system_instruction_handler: &mut InstructionHandler,
    ) -> Result<
        ControlFlow<(), (Self::Reg, <Self::Reg as Register>::Type)>,
        ExecutionError<Reg::Type, CustomError>,
    > {
        match self {
            // Mask-register logical instructions (§16.1).
            // These compute the body elements [vstart, vl); prestart bits [0, vstart) are
            // undisturbed and the tail (past vl) is tail-agnostic (realised here as
            // undisturbed). They still require vtype to be valid (vill=0); any vector
            // instruction must be rejected when vill is set, regardless of whether it uses
            // SEW or vl.
            Self::Vmandn { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: all VReg values are valid indices < 32; `vl <= VLEN` and
                // `vstart <= vl` are architectural invariants; snapshot-before-write inside
                // the helper means vd may overlap vs2 or vs1 safely.
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        a && !b
                    });
                }
            }
            Self::Vmand { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        a & b
                    });
                }
            }
            Self::Vmor { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        a | b
                    });
                }
            }
            Self::Vmxor { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        a ^ b
                    });
                }
            }
            Self::Vmorn { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        a || !b
                    });
                }
            }
            Self::Vmnand { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        !(a & b)
                    });
                }
            }
            Self::Vmnor { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        !(a | b)
                    });
                }
            }
            Self::Vmxnor { vd, vs2, vs1 } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: see `Vmandn`
                unsafe {
                    zvexx_mask_helpers::execute_mask_logical_op(ext_state, vd, vs2, vs1, |a, b| {
                        !(a ^ b)
                    });
                }
            }
            // vcpop.m (§16.2): count set bits in vs2 over active elements, write to GPR rd.
            Self::Vcpop { rd, vs2, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                // vcpop/vfirst require a valid vtype to know vl, but do not use SEW.
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: `vl <= VLMAX <= VLEN`, so `vl.div_ceil(8) <= VLENB`; `vstart <= vl`
                // by spec invariant.
                unsafe {
                    zvexx_mask_helpers::execute_vcpop(regs, ext_state, rd, vs2, vm);
                }
            }
            // vfirst.m (§16.3): find lowest-numbered active set bit in vs2, write index to rd.
            Self::Vfirst { rd, vs2, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // SAFETY: same as `Vcpop`
                unsafe {
                    zvexx_mask_helpers::execute_vfirst(regs, ext_state, rd, vs2, vm);
                }
            }
            // vmsbf.m (§16.4): set-before-first mask bit.
            // Constraints: vd != vs2 (overlap illegal), vm=false implies vd != v0.
            Self::Vmsbf { vd, vs2, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // Spec §16.4: vmsbf/vmsif/vmsof with vstart != 0 raise an illegal instruction
                // exception.
                if ext_state.vstart() != 0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                // Per spec §16.4: vd must not overlap vs2
                if vd == vs2 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if !vm && vd == VReg::V0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let vl = ext_state.vl();
                // SAFETY: `vd != vs2` checked above; `vd != v0` when masked checked above;
                // `vstart == 0` checked above; `vl <= VLEN` so `vl.div_ceil(8) <= VLENB`.
                unsafe {
                    zvexx_mask_helpers::execute_vmsbf(ext_state, vd, vs2, vm, vl);
                }
            }
            // vmsof.m (§16.5): set-only-first mask bit.
            // Same overlap constraints as vmsbf.
            Self::Vmsof { vd, vs2, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // Spec §16.4: vmsbf/vmsif/vmsof with vstart != 0 raise an illegal instruction
                // exception.
                if ext_state.vstart() != 0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if vd == vs2 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if !vm && vd == VReg::V0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let vl = ext_state.vl();
                // SAFETY: see `Vmsbf`
                unsafe {
                    zvexx_mask_helpers::execute_vmsof(ext_state, vd, vs2, vm, vl);
                }
            }
            // vmsif.m (§16.6): set-including-first mask bit.
            // Same overlap constraints as vmsbf.
            Self::Vmsif { vd, vs2, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // Spec §16.4: vmsbf/vmsif/vmsof with vstart != 0 raise an illegal instruction
                // exception.
                if ext_state.vstart() != 0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if vd == vs2 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if !vm && vd == VReg::V0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let vl = ext_state.vl();
                // SAFETY: see `Vmsbf`
                unsafe {
                    zvexx_mask_helpers::execute_vmsif(ext_state, vd, vs2, vm, vl);
                }
            }
            // viota.m (§16.8): write prefix popcount of vs2 bits as SEW-wide elements into vd.
            // Constraints: vd must not overlap vs2 or v0 (when masked); vd alignment per LMUL;
            // vstart must be zero (mandatory trap per spec §16.8). There is no SEW-width
            // constraint: if SEW is too narrow to hold the prefix count the result simply wraps
            // (truncates to SEW), matching the spec's "integer operations wrap around on overflow"
            // rule rather than raising an exception.
            Self::Viota { vd, vs2, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let vtype = ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                // Spec §16.8: viota.m with vstart != 0 raises an illegal instruction exception.
                if ext_state.vstart() != 0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let group_regs = vtype.vlmul().register_count();
                let vd_idx = vd.to_bits();
                if !vd_idx.is_multiple_of(group_regs) || vd_idx + group_regs > 32 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                // vd must not overlap vs2; vs2 is always a single mask register (group size 1).
                let vd_start = u32::from(vd.to_bits());
                let vs2_start = u32::from(vs2.to_bits());
                if vd_start < vs2_start + 1 && vs2_start < vd_start + u32::from(group_regs) {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if !vm && vd == VReg::V0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let sew = vtype.vsew();
                let vl = ext_state.vl();
                // SAFETY: vd alignment checked above; vd group does not overlap vs2 checked above;
                // `vm=false` implies `vd != v0` checked above; vstart == 0 checked above;
                // `vl <= VLMAX = group_regs * VLENB / sew_bytes`, all element indices valid.
                unsafe {
                    zvexx_mask_helpers::execute_viota(ext_state, vd, vs2, vm, vl, sew);
                }
            }
            // vid.v (§16.9): write element index i as SEW-wide integer into vd[i].
            // Constraints: vm=false implies vd != v0; vd alignment per LMUL.
            Self::Vid { vd, vm } => {
                if !ext_state.vector_instructions_allowed() {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let vtype = ext_state
                    .vtype()
                    .ok_or(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    })?;
                let group_regs = vtype.vlmul().register_count();
                let vd_idx = vd.to_bits();
                if !vd_idx.is_multiple_of(group_regs) || vd_idx + group_regs > 32 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                if !vm && vd == VReg::V0 {
                    return Err(ExecutionError::IllegalInstruction {
                        address: program_counter.old_pc(zvexx_helpers::INSTRUCTION_SIZE),
                    });
                }
                let sew = vtype.vsew();
                // SAFETY: vd alignment checked above; `vm=false` implies `vd != v0` checked above;
                // `vl <= VLMAX = group_regs * VLENB / sew_bytes`, all element indices valid.
                unsafe {
                    zvexx_mask_helpers::execute_vid(ext_state, vd, vm, sew);
                }
            }
        }

        Ok(ControlFlow::Continue(Default::default()))
    }
}