ab_riscv_interpreter/rv64/zk/zkn/
zknh.rs

1//! RV64 Zknh extension
2
3pub mod rv64_zknh_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::prelude::*;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
15    for Rv64ZknhInstruction<Reg>
16where
17    Reg: Register<Type = u64>,
18    Regs: RegisterFile<Reg>,
19{
20    #[inline(always)]
21    fn execute(
22        self,
23        regs: &mut Regs,
24        _ext_state: &mut ExtState,
25        _memory: &mut Memory,
26        _program_counter: &mut PC,
27        _system_instruction_handler: &mut InstructionHandler,
28    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
29        match self {
30            Self::Sha256Sig0 { rd, rs1 } => {
31                let x = regs.read(rs1) as u32;
32
33                let res32 = rv64_zknh_helpers::sha256sig0(x);
34
35                regs.write(rd, i64::from(res32.cast_signed()).cast_unsigned());
36            }
37            Self::Sha256Sig1 { rd, rs1 } => {
38                let x = regs.read(rs1) as u32;
39
40                let res32 = rv64_zknh_helpers::sha256sig1(x);
41
42                regs.write(rd, i64::from(res32.cast_signed()).cast_unsigned());
43            }
44            Self::Sha256Sum0 { rd, rs1 } => {
45                let x = regs.read(rs1) as u32;
46
47                let res32 = rv64_zknh_helpers::sha256sum0(x);
48
49                regs.write(rd, i64::from(res32.cast_signed()).cast_unsigned());
50            }
51            Self::Sha256Sum1 { rd, rs1 } => {
52                let x = regs.read(rs1) as u32;
53
54                let res32 = rv64_zknh_helpers::sha256sum1(x);
55
56                regs.write(rd, i64::from(res32.cast_signed()).cast_unsigned());
57            }
58            Self::Sha512Sig0 { rd, rs1 } => {
59                let x = regs.read(rs1);
60
61                regs.write(rd, rv64_zknh_helpers::sha512sig0(x));
62            }
63            Self::Sha512Sig1 { rd, rs1 } => {
64                let x = regs.read(rs1);
65
66                regs.write(rd, rv64_zknh_helpers::sha512sig1(x));
67            }
68            Self::Sha512Sum0 { rd, rs1 } => {
69                let x = regs.read(rs1);
70
71                regs.write(rd, rv64_zknh_helpers::sha512sum0(x));
72            }
73            Self::Sha512Sum1 { rd, rs1 } => {
74                let x = regs.read(rs1);
75
76                regs.write(rd, rv64_zknh_helpers::sha512sum1(x));
77            }
78        }
79
80        Ok(ControlFlow::Continue(()))
81    }
82}
ab_riscv_interpreter/rv64/zk/zkn/zknh.rs

ab_riscv_interpreter/rv64/zk/zkn/
zknh.rs
