ab_riscv_interpreter/rv64/zk/zkn/
zkne.rs1pub mod rv64_zkne_helpers;
4#[cfg(not(all(miri, target_arch = "aarch64")))]
7#[cfg(test)]
8mod tests;
9
10use crate::rv64::zk::zkn::zknd::rv64_zknd_helpers;
11use crate::{
12 ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
13 ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
14 RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
15 ThreadedExecutionResult,
16};
17use ab_riscv_macros::instruction_execution;
18use ab_riscv_primitives::prelude::*;
19
20#[instruction_execution]
21const impl<Reg> ExecutableInstructionOperands for Rv64ZkneInstruction<Reg> where
22 Reg: Register<Type = u64>
23{
24}
25
26#[instruction_execution]
27const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZkneInstruction<Reg> where
28 Reg: Register<Type = u64>
29{
30}
31
32#[instruction_execution]
33const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
34 for Rv64ZkneInstruction<Reg>
35where
36 Reg: [const] Register<Type = u64>,
37 Regs: [const] RegisterFile<Reg>,
38{
39 #[inline(always)]
40 #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
41 fn execute(
42 self,
43 Rs1Rs2OperandValues {
44 rs1_value,
45 rs2_value,
46 }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
47 _regs: &mut Regs,
48 _env: &mut Env,
49 _memory: &mut Memory,
50 _program_counter: &mut PC,
51 ) -> ExecutionResult<Self::Reg> {
52 match self {
53 Self::Aes64Es { rd, rs1: _, rs2: _ } => {
54 let v1 = rs1_value;
55 let v2 = rs2_value;
56 ExecutionResult::Continue {
57 rd,
58 value: rv64_zkne_helpers::aes64es(v1, v2),
59 }
60 }
61 Self::Aes64Esm { rd, rs1: _, rs2: _ } => {
62 let v1 = rs1_value;
63 let v2 = rs2_value;
64 ExecutionResult::Continue {
65 rd,
66 value: rv64_zkne_helpers::aes64esm(v1, v2),
67 }
68 }
69 }
70 }
71}