ab_riscv_interpreter/rv64/zk/zkn/
zkne.rs

1//! RV64 Zkne extension
2
3pub mod rv64_zkne_helpers;
4// TODO: `llvm.aarch64.crypto.aes*` is not supported in Miri yet:
5//  https://github.com/rust-lang/miri/issues/3172#issuecomment-3730602707
6#[cfg(not(all(miri, target_arch = "aarch64")))]
7#[cfg(test)]
8mod tests;
9
10use crate::rv64::zk::zkn::zknd::rv64_zknd_helpers;
11use crate::{
12    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
13    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
14};
15use ab_riscv_macros::instruction_execution;
16use ab_riscv_primitives::prelude::*;
17use core::ops::ControlFlow;
18
19#[instruction_execution]
20impl<Reg> ExecutableInstructionOperands for Rv64ZkneInstruction<Reg> where Reg: Register<Type = u64> {}
21
22#[instruction_execution]
23impl<Reg, ExtState, CustomError> ExecutableInstructionCsr<ExtState, CustomError>
24    for Rv64ZkneInstruction<Reg>
25where
26    Reg: Register<Type = u64>,
27{
28}
29
30#[instruction_execution]
31impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
32    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
33    for Rv64ZkneInstruction<Reg>
34where
35    Reg: Register<Type = u64>,
36    Regs: RegisterFile<Reg>,
37{
38    #[inline(always)]
39    fn execute(
40        self,
41        Rs1Rs2OperandValues {
42            rs1_value,
43            rs2_value,
44        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
45        _regs: &mut Regs,
46        _ext_state: &mut ExtState,
47        _memory: &mut Memory,
48        _program_counter: &mut PC,
49        _system_instruction_handler: &mut InstructionHandler,
50    ) -> Result<
51        ControlFlow<(), (Self::Reg, <Self::Reg as Register>::Type)>,
52        ExecutionError<Reg::Type, CustomError>,
53    > {
54        match self {
55            Self::Aes64Es { rd, rs1: _, rs2: _ } => {
56                let v1 = rs1_value;
57                let v2 = rs2_value;
58                Ok(ControlFlow::Continue((
59                    rd,
60                    rv64_zkne_helpers::aes64es(v1, v2),
61                )))
62            }
63            Self::Aes64Esm { rd, rs1: _, rs2: _ } => {
64                let v1 = rs1_value;
65                let v2 = rs2_value;
66                Ok(ControlFlow::Continue((
67                    rd,
68                    rv64_zkne_helpers::aes64esm(v1, v2),
69                )))
70            }
71        }
72    }
73}
ab_riscv_interpreter/rv64/zk/zkn/zkne.rs

ab_riscv_interpreter/rv64/zk/zkn/
zkne.rs
