ab_riscv_interpreter/rv64/zk/zkn/
zknd.rs

1//! RV64 Zknd extension
2
3pub mod rv64_zknd_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::prelude::*;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
15    for Rv64ZkndInstruction<Reg>
16where
17    Reg: Register<Type = u64>,
18    Regs: RegisterFile<Reg>,
19{
20    #[inline(always)]
21    fn execute(
22        self,
23        regs: &mut Regs,
24        _ext_state: &mut ExtState,
25        _memory: &mut Memory,
26        _program_counter: &mut PC,
27        _system_instruction_handler: &mut InstructionHandler,
28    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
29        match self {
30            Self::Aes64Ds { rd, rs1, rs2 } => {
31                let v1 = regs.read(rs1);
32                let v2 = regs.read(rs2);
33                regs.write(rd, rv64_zknd_helpers::aes64ds(v1, v2));
34            }
35            Self::Aes64Dsm { rd, rs1, rs2 } => {
36                let v1 = regs.read(rs1);
37                let v2 = regs.read(rs2);
38                regs.write(rd, rv64_zknd_helpers::aes64dsm(v1, v2));
39            }
40            Self::Aes64Im { rd, rs1 } => {
41                let v1 = regs.read(rs1);
42                regs.write(rd, rv64_zknd_helpers::aes64im(v1));
43            }
44            Self::Aes64Ks1i { rd, rs1, rnum } => {
45                let v1 = regs.read(rs1);
46                regs.write(rd, rv64_zknd_helpers::aes64ks1i(v1, rnum));
47            }
48            Self::Aes64Ks2 { rd, rs1, rs2 } => {
49                let v1 = regs.read(rs1);
50                let v2 = regs.read(rs2);
51                regs.write(rd, rv64_zknd_helpers::aes64ks2(v1, v2));
52            }
53        }
54
55        Ok(ControlFlow::Continue(()))
56    }
57}
ab_riscv_interpreter/rv64/zk/zkn/zknd.rs

ab_riscv_interpreter/rv64/zk/zkn/
zknd.rs
