ab_riscv_interpreter/rv64/
zacas.rs

1//! RV64 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::rv32::a::amo_helpers;
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
10    PackedAddress, RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
11    ThreadedExecutableInstruction, ThreadedExecutionResult, VirtualMemory,
12};
13use ab_riscv_macros::instruction_execution;
14use ab_riscv_primitives::prelude::*;
15
16#[instruction_execution]
17const impl<Reg, Hart> ExecutableInstructionOperands for Rv64ZacasInstruction<Hart>
18where
19    Reg: Register<Type = u64>,
20    Hart: HartConfig<Reg = Reg>,
21{
22}
23
24#[instruction_execution]
25const impl<Reg, Hart, Env> ExecutableInstructionCsr<Env> for Rv64ZacasInstruction<Hart>
26where
27    Reg: Register<Type = u64>,
28    Hart: HartConfig<Reg = Reg>,
29{
30}
31
32#[instruction_execution]
33const impl<Reg, Hart, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
34    for Rv64ZacasInstruction<Hart>
35where
36    Reg: [const] Register<Type = u64>,
37    Hart: HartConfig<Reg = Reg>,
38    Regs: [const] RegisterFile<Reg>,
39    Memory: [const] VirtualMemory,
40{
41    #[inline(always)]
42    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
43    fn execute(
44        self,
45        Rs1Rs2OperandValues {
46            rs1_value,
47            rs2_value,
48        }: Rs1Rs2OperandValues<Reg::Type>,
49        regs: &mut Regs,
50        _env: &mut Env,
51        memory: &mut Memory,
52        _program_counter: &PC,
53    ) -> ExecutionResult<Reg> {
54        match self {
55            Self::AmocasW {
56                rd,
57                rs1: _,
58                rs2: _,
59                aq: _,
60                rl: _,
61            } => {
62                let addr = rs1_value;
63                // The 4-byte access must not cross a misaligned atomicity granule (4096 bytes)
64                // boundary
65                if addr / 4096 != (addr + 3) / 4096 {
66                    ::core::hint::cold_path();
67                    return ExecutionResult::Err(ExecutionError::MisalignedAtomic {
68                        address: PackedAddress::new(addr),
69                    });
70                }
71                // Ignore the upper bits of `rd` when comparing, per spec
72                let compare = regs.read(rd) as u32;
73                let old = amo_helpers::amo_read::<i32, _, _>(memory, addr)?;
74                if old.cast_unsigned() == compare {
75                    memory.write(addr, rs2_value as u32)?;
76                }
77                ExecutionResult::Continue {
78                    rd,
79                    value: i64::from(old).cast_unsigned(),
80                }
81            }
82            Self::AmocasD {
83                rd,
84                rs1: _,
85                rs2: _,
86                aq: _,
87                rl: _,
88            } => {
89                let addr = rs1_value;
90                // The 8-byte access must not cross a misaligned atomicity granule (4096 bytes)
91                // boundary
92                if addr / 4096 != (addr + 7) / 4096 {
93                    ::core::hint::cold_path();
94                    return ExecutionResult::Err(ExecutionError::MisalignedAtomic {
95                        address: PackedAddress::new(addr),
96                    });
97                }
98                let compare = regs.read(rd);
99                let old = amo_helpers::amo_read::<u64, _, _>(memory, addr)?;
100                if old == compare {
101                    memory.write(addr, rs2_value)?;
102                }
103                ExecutionResult::Continue { rd, value: old }
104            }
105            Self::AmocasQ {
106                rd,
107                rs1: _,
108                rs2,
109                rd_hi,
110                rs2_hi,
111                aq: _,
112                rl: _,
113            } => {
114                let addr = rs1_value;
115                // The 16-byte access must not cross a misaligned atomicity granule (4096 bytes)
116                // boundary
117                if addr / 4096 != (addr + 15) / 4096 {
118                    ::core::hint::cold_path();
119                    return ExecutionResult::Err(ExecutionError::MisalignedAtomic {
120                        address: PackedAddress::new(addr),
121                    });
122                }
123                // Per spec, when the first register of a pair is `x0`, BOTH halves of that pair
124                // read as zero - not just the literal `x0` half. `compare_lo`/`rs2_value` are
125                // already 0 in that case since `x0` is hardwired, but `compare_hi`/`swap_hi`
126                // need an explicit override since `rd_hi`/`rs2_hi` are real registers.
127                let compare_lo = regs.read(rd);
128                let compare_hi = if rd == Reg::ZERO { 0 } else { regs.read(rd_hi) };
129                let swap_hi = if rs2 == Reg::ZERO {
130                    0
131                } else {
132                    regs.read(rs2_hi)
133                };
134                let old_lo = amo_helpers::amo_read::<u64, _, _>(memory, addr)?;
135                let old_hi = amo_helpers::amo_read::<u64, _, _>(memory, addr + 8)?;
136                if old_lo == compare_lo && old_hi == compare_hi {
137                    memory.write(addr, rs2_value)?;
138                    memory.write(addr + 8, swap_hi)?;
139                }
140                // Per spec, when `rd == x0` the whole register-pair write (both halves) is
141                // skipped, not just the low half (which is a no-op anyway since x0 is
142                // hardwired). Only `rd_hi` needs an explicit guard since it's a real register.
143                if rd != Reg::ZERO {
144                    regs.write(rd_hi, old_hi);
145                }
146                ExecutionResult::Continue { rd, value: old_lo }
147            }
148        }
149    }
150}
ab_riscv_interpreter/rv64/zacas.rs

ab_riscv_interpreter/rv64/
zacas.rs
