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ab_riscv_interpreter/rv64/m/
zmmul.rs

1//! RV64 Zmmul extension (multiplication subset of M extension)
2
3use crate::{
4    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
5    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
6    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
7    ThreadedExecutionResult,
8};
9use ab_riscv_macros::instruction_execution;
10use ab_riscv_primitives::prelude::*;
11
12#[instruction_execution]
13const impl<Reg> ExecutableInstructionOperands for Rv64ZmmulInstruction<Reg> where
14    Reg: Register<Type = u64>
15{
16}
17
18#[instruction_execution]
19const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZmmulInstruction<Reg> where
20    Reg: Register<Type = u64>
21{
22}
23
24#[instruction_execution]
25const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
26    for Rv64ZmmulInstruction<Reg>
27where
28    Reg: [const] Register<Type = u64>,
29{
30    #[inline(always)]
31    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
32    fn execute(
33        self,
34        Rs1Rs2OperandValues {
35            rs1_value,
36            rs2_value,
37        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
38        _regs: &mut Regs,
39        _env: &mut Env,
40        _memory: &mut Memory,
41        _program_counter: &mut PC,
42    ) -> ExecutionResult<Self::Reg> {
43        ExecutionResult::ContinueNoWrite
44    }
45}