ab_riscv_interpreter/rv64/
m.rs

1//! RV64 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::prelude::*;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
15    for Rv64MInstruction<Reg>
16where
17    Reg: Register<Type = u64>,
18    Regs: RegisterFile<Reg>,
19{
20    #[inline(always)]
21    fn execute(
22        self,
23        regs: &mut Regs,
24        _ext_state: &mut ExtState,
25        _memory: &mut Memory,
26        _program_counter: &mut PC,
27        _system_instruction_handler: &mut InstructionHandler,
28    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
29        match self {
30            Self::Mul { rd, rs1, rs2 } => {
31                let value = regs.read(rs1).wrapping_mul(regs.read(rs2));
32                regs.write(rd, value);
33            }
34            Self::Mulh { rd, rs1, rs2 } => {
35                // Signed × signed: widen to i128, take upper 64 bits
36                let (_lo, prod) = regs
37                    .read(rs1)
38                    .cast_signed()
39                    .widening_mul(regs.read(rs2).cast_signed());
40                regs.write(rd, prod.cast_unsigned());
41            }
42            Self::Mulhsu { rd, rs1, rs2 } => {
43                // Signed × unsigned: widen to i128, take upper 64 bits
44                let prod = i128::from(regs.read(rs1).cast_signed()) * i128::from(regs.read(rs2));
45                let value = prod >> 64;
46                regs.write(rd, value.cast_unsigned() as u64);
47            }
48            Self::Mulhu { rd, rs1, rs2 } => {
49                // Unsigned × unsigned: widen to u128, take upper 64 bits
50                let prod = u128::from(regs.read(rs1)) * u128::from(regs.read(rs2));
51                let value = prod >> 64;
52                regs.write(rd, value as u64);
53            }
54            Self::Div { rd, rs1, rs2 } => {
55                let dividend = regs.read(rs1).cast_signed();
56                let divisor = regs.read(rs2).cast_signed();
57                let value = if divisor == 0 {
58                    -1i64
59                } else if dividend == i64::MIN && divisor == -1 {
60                    i64::MIN
61                } else {
62                    dividend / divisor
63                };
64                regs.write(rd, value.cast_unsigned());
65            }
66            Self::Divu { rd, rs1, rs2 } => {
67                let dividend = regs.read(rs1);
68                let divisor = regs.read(rs2);
69                let value = dividend.checked_div(divisor).unwrap_or(u64::MAX);
70                regs.write(rd, value);
71            }
72            Self::Rem { rd, rs1, rs2 } => {
73                let dividend = regs.read(rs1).cast_signed();
74                let divisor = regs.read(rs2).cast_signed();
75                let value = if divisor == 0 {
76                    dividend
77                } else if dividend == i64::MIN && divisor == -1 {
78                    0
79                } else {
80                    dividend % divisor
81                };
82                regs.write(rd, value.cast_unsigned());
83            }
84            Self::Remu { rd, rs1, rs2 } => {
85                let dividend = regs.read(rs1);
86                let divisor = regs.read(rs2);
87                let value = if divisor == 0 {
88                    dividend
89                } else {
90                    dividend % divisor
91                };
92                regs.write(rd, value);
93            }
94
95            // RV64 R-type W
96            Self::Mulw { rd, rs1, rs2 } => {
97                let prod = (regs.read(rs1) as i32).wrapping_mul(regs.read(rs2) as i32);
98                regs.write(rd, (prod as i64).cast_unsigned());
99            }
100            Self::Divw { rd, rs1, rs2 } => {
101                let dividend = regs.read(rs1) as i32;
102                let divisor = regs.read(rs2) as i32;
103                let value = if divisor == 0 {
104                    -1i64
105                } else if dividend == i32::MIN && divisor == -1 {
106                    i64::from(i32::MIN)
107                } else {
108                    i64::from(dividend / divisor)
109                };
110                regs.write(rd, value.cast_unsigned());
111            }
112            Self::Divuw { rd, rs1, rs2 } => {
113                let dividend = regs.read(rs1) as u32;
114                let divisor = regs.read(rs2) as u32;
115                let value = dividend.checked_div(divisor).map_or(u64::MAX, |value| {
116                    i64::from(value.cast_signed()).cast_unsigned()
117                });
118                regs.write(rd, value);
119            }
120            Self::Remw { rd, rs1, rs2 } => {
121                let dividend = regs.read(rs1) as i32;
122                let divisor = regs.read(rs2) as i32;
123                let value = if divisor == 0 {
124                    (dividend as i64).cast_unsigned()
125                } else if dividend == i32::MIN && divisor == -1 {
126                    0
127                } else {
128                    ((dividend % divisor) as i64).cast_unsigned()
129                };
130                regs.write(rd, value);
131            }
132            Self::Remuw { rd, rs1, rs2 } => {
133                let dividend = regs.read(rs1) as u32;
134                let divisor = regs.read(rs2) as u32;
135                let value = if divisor == 0 {
136                    dividend.cast_signed() as i64
137                } else {
138                    (dividend % divisor).cast_signed() as i64
139                };
140                regs.write(rd, value.cast_unsigned());
141            }
142        }
143
144        Ok(ControlFlow::Continue(()))
145    }
146}
ab_riscv_interpreter/rv64/m.rs

ab_riscv_interpreter/rv64/
m.rs
