ab_riscv_interpreter/rv64/
m.rs

1//! RV64 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
10};
11use ab_riscv_macros::instruction_execution;
12use ab_riscv_primitives::prelude::*;
13use core::ops::ControlFlow;
14
15#[instruction_execution]
16impl<Reg> ExecutableInstructionOperands for Rv64MInstruction<Reg> where Reg: Register<Type = u64> {}
17
18#[instruction_execution]
19impl<Reg, ExtState, CustomError> ExecutableInstructionCsr<ExtState, CustomError>
20    for Rv64MInstruction<Reg>
21where
22    Reg: Register<Type = u64>,
23{
24}
25
26#[instruction_execution]
27impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
28    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
29    for Rv64MInstruction<Reg>
30where
31    Reg: Register<Type = u64>,
32    Regs: RegisterFile<Reg>,
33{
34    #[inline(always)]
35    fn execute(
36        self,
37        Rs1Rs2OperandValues {
38            rs1_value,
39            rs2_value,
40        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
41        _regs: &mut Regs,
42        _ext_state: &mut ExtState,
43        _memory: &mut Memory,
44        _program_counter: &mut PC,
45        _system_instruction_handler: &mut InstructionHandler,
46    ) -> Result<
47        ControlFlow<(), (Self::Reg, <Self::Reg as Register>::Type)>,
48        ExecutionError<Reg::Type, CustomError>,
49    > {
50        match self {
51            Self::Mul { rd, rs1: _, rs2: _ } => {
52                let value = rs1_value.wrapping_mul(rs2_value);
53                Ok(ControlFlow::Continue((rd, value)))
54            }
55            Self::Mulh { rd, rs1: _, rs2: _ } => {
56                // Signed × signed: widen to i128, take upper 64 bits
57                let (_lo, prod) = rs1_value
58                    .cast_signed()
59                    .widening_mul(rs2_value.cast_signed());
60                Ok(ControlFlow::Continue((rd, prod.cast_unsigned())))
61            }
62            Self::Mulhsu { rd, rs1: _, rs2: _ } => {
63                // Signed × unsigned: widen to i128, take upper 64 bits
64                let prod = i128::from(rs1_value.cast_signed()) * i128::from(rs2_value);
65                let value = prod >> 64;
66                Ok(ControlFlow::Continue((rd, value.cast_unsigned() as u64)))
67            }
68            Self::Mulhu { rd, rs1: _, rs2: _ } => {
69                // Unsigned × unsigned: widen to u128, take upper 64 bits
70                let prod = u128::from(rs1_value) * u128::from(rs2_value);
71                let value = prod >> 64;
72                Ok(ControlFlow::Continue((rd, value as u64)))
73            }
74            Self::Div { rd, rs1: _, rs2: _ } => {
75                let dividend = rs1_value.cast_signed();
76                let divisor = rs2_value.cast_signed();
77                let value = if divisor == 0 {
78                    -1i64
79                } else if dividend == i64::MIN && divisor == -1 {
80                    i64::MIN
81                } else {
82                    dividend / divisor
83                };
84                Ok(ControlFlow::Continue((rd, value.cast_unsigned())))
85            }
86            Self::Divu { rd, rs1: _, rs2: _ } => {
87                let dividend = rs1_value;
88                let divisor = rs2_value;
89                let value = dividend.checked_div(divisor).unwrap_or(u64::MAX);
90                Ok(ControlFlow::Continue((rd, value)))
91            }
92            Self::Rem { rd, rs1: _, rs2: _ } => {
93                let dividend = rs1_value.cast_signed();
94                let divisor = rs2_value.cast_signed();
95                let value = if divisor == 0 {
96                    dividend
97                } else if dividend == i64::MIN && divisor == -1 {
98                    0
99                } else {
100                    dividend % divisor
101                };
102                Ok(ControlFlow::Continue((rd, value.cast_unsigned())))
103            }
104            Self::Remu { rd, rs1: _, rs2: _ } => {
105                let dividend = rs1_value;
106                let divisor = rs2_value;
107                let value = if divisor == 0 {
108                    dividend
109                } else {
110                    dividend % divisor
111                };
112                Ok(ControlFlow::Continue((rd, value)))
113            }
114
115            // RV64 R-type W
116            Self::Mulw { rd, rs1: _, rs2: _ } => {
117                let prod = (rs1_value as i32).wrapping_mul(rs2_value as i32);
118                Ok(ControlFlow::Continue((rd, (prod as i64).cast_unsigned())))
119            }
120            Self::Divw { rd, rs1: _, rs2: _ } => {
121                let dividend = rs1_value as i32;
122                let divisor = rs2_value as i32;
123                let value = if divisor == 0 {
124                    -1i64
125                } else if dividend == i32::MIN && divisor == -1 {
126                    i64::from(i32::MIN)
127                } else {
128                    i64::from(dividend / divisor)
129                };
130                Ok(ControlFlow::Continue((rd, value.cast_unsigned())))
131            }
132            Self::Divuw { rd, rs1: _, rs2: _ } => {
133                let dividend = rs1_value as u32;
134                let divisor = rs2_value as u32;
135                let value = dividend.checked_div(divisor).map_or(u64::MAX, |value| {
136                    i64::from(value.cast_signed()).cast_unsigned()
137                });
138                Ok(ControlFlow::Continue((rd, value)))
139            }
140            Self::Remw { rd, rs1: _, rs2: _ } => {
141                let dividend = rs1_value as i32;
142                let divisor = rs2_value as i32;
143                let value = if divisor == 0 {
144                    (dividend as i64).cast_unsigned()
145                } else if dividend == i32::MIN && divisor == -1 {
146                    0
147                } else {
148                    ((dividend % divisor) as i64).cast_unsigned()
149                };
150                Ok(ControlFlow::Continue((rd, value)))
151            }
152            Self::Remuw { rd, rs1: _, rs2: _ } => {
153                let dividend = rs1_value as u32;
154                let divisor = rs2_value as u32;
155                let value = if divisor == 0 {
156                    dividend.cast_signed() as i64
157                } else {
158                    (dividend % divisor).cast_signed() as i64
159                };
160                Ok(ControlFlow::Continue((rd, value.cast_unsigned())))
161            }
162        }
163    }
164}
ab_riscv_interpreter/rv64/m.rs

ab_riscv_interpreter/rv64/
m.rs
