ab_riscv_interpreter/rv64/b/
zbs.rs

1//! RV64 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::rv64::Rv64InterpreterState;
7use crate::{ExecutableInstruction, ExecutionError};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::instruction::rv64::b::zbs::Rv64ZbsInstruction;
10use ab_riscv_primitives::registers::Register;
11use core::ops::ControlFlow;
12
13#[instruction_execution]
14impl<Reg, Memory, PC, InstructionHandler, CustomError>
15    ExecutableInstruction<
16        Rv64InterpreterState<Reg, Memory, PC, InstructionHandler, CustomError>,
17        CustomError,
18    > for Rv64ZbsInstruction<Reg>
19where
20    Reg: Register<Type = u64>,
21    [(); Reg::N]:,
22{
23    #[inline(always)]
24    fn execute(
25        self,
26        state: &mut Rv64InterpreterState<Reg, Memory, PC, InstructionHandler, CustomError>,
27    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, Self, CustomError>> {
28        match self {
29            Self::Bset { rd, rs1, rs2 } => {
30                // Only the bottom 6 bits for RV64
31                let index = state.regs.read(rs2) & 0x3f;
32                let result = state.regs.read(rs1) | (1u64 << index);
33                state.regs.write(rd, result);
34            }
35            Self::Bseti { rd, rs1, shamt } => {
36                let index = shamt;
37                let result = state.regs.read(rs1) | (1u64 << index);
38                state.regs.write(rd, result);
39            }
40            Self::Bclr { rd, rs1, rs2 } => {
41                let index = state.regs.read(rs2) & 0x3f;
42                let result = state.regs.read(rs1) & !(1u64 << index);
43                state.regs.write(rd, result);
44            }
45            Self::Bclri { rd, rs1, shamt } => {
46                let index = shamt;
47                let result = state.regs.read(rs1) & !(1u64 << index);
48                state.regs.write(rd, result);
49            }
50            Self::Binv { rd, rs1, rs2 } => {
51                let index = state.regs.read(rs2) & 0x3f;
52                let result = state.regs.read(rs1) ^ (1u64 << index);
53                state.regs.write(rd, result);
54            }
55            Self::Binvi { rd, rs1, shamt } => {
56                let index = shamt;
57                let result = state.regs.read(rs1) ^ (1u64 << index);
58                state.regs.write(rd, result);
59            }
60            Self::Bext { rd, rs1, rs2 } => {
61                let index = state.regs.read(rs2) & 0x3f;
62                let result = (state.regs.read(rs1) >> index) & 1;
63                state.regs.write(rd, result);
64            }
65            Self::Bexti { rd, rs1, shamt } => {
66                let index = shamt;
67                let result = (state.regs.read(rs1) >> index) & 1;
68                state.regs.write(rd, result);
69            }
70        }
71
72        Ok(ControlFlow::Continue(()))
73    }
74}
ab_riscv_interpreter/rv64/b/zbs.rs

ab_riscv_interpreter/rv64/b/
zbs.rs
