ab_riscv_interpreter/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::rv64::Rv64InterpreterState;
7use crate::{ExecutableInstruction, ExecutionError};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::instruction::rv64::b::zba::Rv64ZbaInstruction;
10use ab_riscv_primitives::registers::Register;
11use core::ops::ControlFlow;
12
13#[instruction_execution]
14impl<Reg, Memory, PC, InstructionHandler, CustomError>
15    ExecutableInstruction<
16        Rv64InterpreterState<Reg, Memory, PC, InstructionHandler, CustomError>,
17        CustomError,
18    > for Rv64ZbaInstruction<Reg>
19where
20    Reg: Register<Type = u64>,
21    [(); Reg::N]:,
22{
23    #[inline(always)]
24    fn execute(
25        self,
26        state: &mut Rv64InterpreterState<Reg, Memory, PC, InstructionHandler, CustomError>,
27    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, Self, CustomError>> {
28        match self {
29            Self::AddUw { rd, rs1, rs2 } => {
30                let rs1_val = (state.regs.read(rs1) as u32) as u64;
31                let value = rs1_val.wrapping_add(state.regs.read(rs2));
32                state.regs.write(rd, value);
33            }
34            Self::Sh1add { rd, rs1, rs2 } => {
35                let value = (state.regs.read(rs1) << 1).wrapping_add(state.regs.read(rs2));
36                state.regs.write(rd, value);
37            }
38            Self::Sh1addUw { rd, rs1, rs2 } => {
39                let rs1_val = (state.regs.read(rs1) as u32) as u64;
40                let value = (rs1_val << 1).wrapping_add(state.regs.read(rs2));
41                state.regs.write(rd, value);
42            }
43            Self::Sh2add { rd, rs1, rs2 } => {
44                let value = (state.regs.read(rs1) << 2).wrapping_add(state.regs.read(rs2));
45                state.regs.write(rd, value);
46            }
47            Self::Sh2addUw { rd, rs1, rs2 } => {
48                let rs1_val = (state.regs.read(rs1) as u32) as u64;
49                let value = (rs1_val << 2).wrapping_add(state.regs.read(rs2));
50                state.regs.write(rd, value);
51            }
52            Self::Sh3add { rd, rs1, rs2 } => {
53                let value = (state.regs.read(rs1) << 3).wrapping_add(state.regs.read(rs2));
54                state.regs.write(rd, value);
55            }
56            Self::Sh3addUw { rd, rs1, rs2 } => {
57                let rs1_val = (state.regs.read(rs1) as u32) as u64;
58                let value = (rs1_val << 3).wrapping_add(state.regs.read(rs2));
59                state.regs.write(rd, value);
60            }
61            Self::SlliUw { rd, rs1, shamt } => {
62                let rs1_val = (state.regs.read(rs1) as u32) as u64;
63                let value = rs1_val << (shamt & 0x3f);
64                state.regs.write(rd, value);
65            }
66        }
67
68        Ok(ControlFlow::Continue(()))
69    }
70}
ab_riscv_interpreter/rv64/b/zba.rs

ab_riscv_interpreter/rv64/b/
zba.rs
