ab_riscv_interpreter/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
7use ab_riscv_macros::instruction_execution;
8use ab_riscv_primitives::prelude::*;
9use core::ops::ControlFlow;
10
11#[instruction_execution]
12impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
13    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    for Rv64ZbaInstruction<Reg>
15where
16    Reg: Register<Type = u64>,
17    Regs: RegisterFile<Reg>,
18{
19    #[inline(always)]
20    fn execute(
21        self,
22        regs: &mut Regs,
23        _ext_state: &mut ExtState,
24        _memory: &mut Memory,
25        _program_counter: &mut PC,
26        _system_instruction_handler: &mut InstructionHandler,
27    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
28        match self {
29            Self::AddUw { rd, rs1, rs2 } => {
30                let rs1_val = (regs.read(rs1) as u32) as u64;
31                let value = rs1_val.wrapping_add(regs.read(rs2));
32                regs.write(rd, value);
33            }
34            Self::Sh1add { rd, rs1, rs2 } => {
35                let value = (regs.read(rs1) << 1).wrapping_add(regs.read(rs2));
36                regs.write(rd, value);
37            }
38            Self::Sh1addUw { rd, rs1, rs2 } => {
39                let rs1_val = (regs.read(rs1) as u32) as u64;
40                let value = (rs1_val << 1).wrapping_add(regs.read(rs2));
41                regs.write(rd, value);
42            }
43            Self::Sh2add { rd, rs1, rs2 } => {
44                let value = (regs.read(rs1) << 2).wrapping_add(regs.read(rs2));
45                regs.write(rd, value);
46            }
47            Self::Sh2addUw { rd, rs1, rs2 } => {
48                let rs1_val = (regs.read(rs1) as u32) as u64;
49                let value = (rs1_val << 2).wrapping_add(regs.read(rs2));
50                regs.write(rd, value);
51            }
52            Self::Sh3add { rd, rs1, rs2 } => {
53                let value = (regs.read(rs1) << 3).wrapping_add(regs.read(rs2));
54                regs.write(rd, value);
55            }
56            Self::Sh3addUw { rd, rs1, rs2 } => {
57                let rs1_val = (regs.read(rs1) as u32) as u64;
58                let value = (rs1_val << 3).wrapping_add(regs.read(rs2));
59                regs.write(rd, value);
60            }
61            Self::SlliUw { rd, rs1, shamt } => {
62                let rs1_val = (regs.read(rs1) as u32) as u64;
63                let value = rs1_val << (shamt & 0x3f);
64                regs.write(rd, value);
65            }
66        }
67
68        Ok(ControlFlow::Continue(()))
69    }
70}
ab_riscv_interpreter/rv64/b/zba.rs

ab_riscv_interpreter/rv64/b/
zba.rs
