ab_riscv_interpreter/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{ExecutableInstruction, ExecutionError, InterpreterState};
7use ab_riscv_macros::instruction_execution;
8use ab_riscv_primitives::instructions::rv64::b::zba::Rv64ZbaInstruction;
9use ab_riscv_primitives::registers::general_purpose::Register;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<
15        InterpreterState<Reg, ExtState, Memory, PC, InstructionHandler, CustomError>,
16        CustomError,
17    > for Rv64ZbaInstruction<Reg>
18where
19    Reg: Register<Type = u64>,
20    [(); Reg::N]:,
21{
22    #[inline(always)]
23    fn execute(
24        self,
25        state: &mut InterpreterState<Reg, ExtState, Memory, PC, InstructionHandler, CustomError>,
26    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
27        match self {
28            Self::AddUw { rd, rs1, rs2 } => {
29                let rs1_val = (state.regs.read(rs1) as u32) as u64;
30                let value = rs1_val.wrapping_add(state.regs.read(rs2));
31                state.regs.write(rd, value);
32            }
33            Self::Sh1add { rd, rs1, rs2 } => {
34                let value = (state.regs.read(rs1) << 1).wrapping_add(state.regs.read(rs2));
35                state.regs.write(rd, value);
36            }
37            Self::Sh1addUw { rd, rs1, rs2 } => {
38                let rs1_val = (state.regs.read(rs1) as u32) as u64;
39                let value = (rs1_val << 1).wrapping_add(state.regs.read(rs2));
40                state.regs.write(rd, value);
41            }
42            Self::Sh2add { rd, rs1, rs2 } => {
43                let value = (state.regs.read(rs1) << 2).wrapping_add(state.regs.read(rs2));
44                state.regs.write(rd, value);
45            }
46            Self::Sh2addUw { rd, rs1, rs2 } => {
47                let rs1_val = (state.regs.read(rs1) as u32) as u64;
48                let value = (rs1_val << 2).wrapping_add(state.regs.read(rs2));
49                state.regs.write(rd, value);
50            }
51            Self::Sh3add { rd, rs1, rs2 } => {
52                let value = (state.regs.read(rs1) << 3).wrapping_add(state.regs.read(rs2));
53                state.regs.write(rd, value);
54            }
55            Self::Sh3addUw { rd, rs1, rs2 } => {
56                let rs1_val = (state.regs.read(rs1) as u32) as u64;
57                let value = (rs1_val << 3).wrapping_add(state.regs.read(rs2));
58                state.regs.write(rd, value);
59            }
60            Self::SlliUw { rd, rs1, shamt } => {
61                let rs1_val = (state.regs.read(rs1) as u32) as u64;
62                let value = rs1_val << (shamt & 0x3f);
63                state.regs.write(rd, value);
64            }
65        }
66
67        Ok(ControlFlow::Continue(()))
68    }
69}
ab_riscv_interpreter/rv64/b/zba.rs

ab_riscv_interpreter/rv64/b/
zba.rs
