ab_riscv_interpreter/rv64/b/
zba.rs

1//! RV64 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{
7    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
8    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
10    ThreadedExecutionResult,
11};
12use ab_riscv_macros::instruction_execution;
13use ab_riscv_primitives::prelude::*;
14
15#[instruction_execution]
16const impl<Reg> ExecutableInstructionOperands for Rv64ZbaInstruction<Reg> where
17    Reg: Register<Type = u64>
18{
19}
20
21#[instruction_execution]
22const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv64ZbaInstruction<Reg> where
23    Reg: Register<Type = u64>
24{
25}
26
27#[instruction_execution]
28const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
29    for Rv64ZbaInstruction<Reg>
30where
31    Reg: [const] Register<Type = u64>,
32    Regs: [const] RegisterFile<Reg>,
33{
34    #[inline(always)]
35    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
36    fn execute(
37        self,
38        Rs1Rs2OperandValues {
39            rs1_value,
40            rs2_value,
41        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
42        _regs: &mut Regs,
43        _env: &mut Env,
44        _memory: &mut Memory,
45        _program_counter: &mut PC,
46    ) -> ExecutionResult<Self::Reg> {
47        match self {
48            Self::AddUw { rd, rs1: _, rs2: _ } => {
49                let rs1_val = u64::from(rs1_value as u32);
50                let value = rs1_val.wrapping_add(rs2_value);
51                ExecutionResult::Continue { rd, value }
52            }
53            Self::Sh1add { rd, rs1: _, rs2: _ } => {
54                let value = (rs1_value << 1).wrapping_add(rs2_value);
55                ExecutionResult::Continue { rd, value }
56            }
57            Self::Sh1addUw { rd, rs1: _, rs2: _ } => {
58                let rs1_val = u64::from(rs1_value as u32);
59                let value = (rs1_val << 1).wrapping_add(rs2_value);
60                ExecutionResult::Continue { rd, value }
61            }
62            Self::Sh2add { rd, rs1: _, rs2: _ } => {
63                let value = (rs1_value << 2).wrapping_add(rs2_value);
64                ExecutionResult::Continue { rd, value }
65            }
66            Self::Sh2addUw { rd, rs1: _, rs2: _ } => {
67                let rs1_val = u64::from(rs1_value as u32);
68                let value = (rs1_val << 2).wrapping_add(rs2_value);
69                ExecutionResult::Continue { rd, value }
70            }
71            Self::Sh3add { rd, rs1: _, rs2: _ } => {
72                let value = (rs1_value << 3).wrapping_add(rs2_value);
73                ExecutionResult::Continue { rd, value }
74            }
75            Self::Sh3addUw { rd, rs1: _, rs2: _ } => {
76                let rs1_val = u64::from(rs1_value as u32);
77                let value = (rs1_val << 3).wrapping_add(rs2_value);
78                ExecutionResult::Continue { rd, value }
79            }
80            Self::SlliUw { rd, rs1: _, shamt } => {
81                let rs1_val = u64::from(rs1_value as u32);
82                let value = rs1_val << (shamt & 0x3f);
83                ExecutionResult::Continue { rd, value }
84            }
85        }
86    }
87}
ab_riscv_interpreter/rv64/b/zba.rs

ab_riscv_interpreter/rv64/b/
zba.rs
