ab_riscv_interpreter/rv32/zk/zkn/
zknd.rs

1//! RV32 Zknd extension
2
3pub mod rv32_zknd_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
10    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
11    ThreadedExecutionResult,
12};
13use ab_riscv_macros::instruction_execution;
14use ab_riscv_primitives::prelude::*;
15
16#[instruction_execution]
17const impl<Reg> ExecutableInstructionOperands for Rv32ZkndInstruction<Reg> where
18    Reg: Register<Type = u32>
19{
20}
21
22#[instruction_execution]
23const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZkndInstruction<Reg> where
24    Reg: Register<Type = u32>
25{
26}
27
28#[instruction_execution]
29const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
30    for Rv32ZkndInstruction<Reg>
31where
32    Reg: [const] Register<Type = u32>,
33    Regs: [const] RegisterFile<Reg>,
34{
35    #[inline(always)]
36    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
37    fn execute(
38        self,
39        Rs1Rs2OperandValues {
40            rs1_value,
41            rs2_value,
42        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
43        _regs: &mut Regs,
44        _env: &mut Env,
45        _memory: &mut Memory,
46        _program_counter: &mut PC,
47    ) -> ExecutionResult<Self::Reg> {
48        match self {
49            Self::Aes32Dsi {
50                rd,
51                rs1: _,
52                rs2: _,
53                bs,
54            } => {
55                let v1 = rs1_value;
56                let v2 = rs2_value;
57                ExecutionResult::Continue {
58                    rd,
59                    value: rv32_zknd_helpers::aes32dsi(v1, v2, bs),
60                }
61            }
62            Self::Aes32Dsmi {
63                rd,
64                rs1: _,
65                rs2: _,
66                bs,
67            } => {
68                let v1 = rs1_value;
69                let v2 = rs2_value;
70                ExecutionResult::Continue {
71                    rd,
72                    value: rv32_zknd_helpers::aes32dsmi(v1, v2, bs),
73                }
74            }
75        }
76    }
77}
ab_riscv_interpreter/rv32/zk/zkn/zknd.rs

ab_riscv_interpreter/rv32/zk/zkn/
zknd.rs
