ab_riscv_interpreter/rv32/zk/zkn/
zknd.rs

1//! RV32 Zknd extension
2
3pub mod rv32_zknd_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
10};
11use ab_riscv_macros::instruction_execution;
12use ab_riscv_primitives::prelude::*;
13use core::ops::ControlFlow;
14
15#[instruction_execution]
16impl<Reg> ExecutableInstructionOperands for Rv32ZkndInstruction<Reg> where Reg: Register<Type = u32> {}
17
18#[instruction_execution]
19impl<Reg, ExtState, CustomError> ExecutableInstructionCsr<ExtState, CustomError>
20    for Rv32ZkndInstruction<Reg>
21where
22    Reg: Register<Type = u32>,
23{
24}
25
26#[instruction_execution]
27impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
28    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
29    for Rv32ZkndInstruction<Reg>
30where
31    Reg: Register<Type = u32>,
32    Regs: RegisterFile<Reg>,
33{
34    #[inline(always)]
35    fn execute(
36        self,
37        Rs1Rs2OperandValues {
38            rs1_value,
39            rs2_value,
40        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
41        _regs: &mut Regs,
42        _ext_state: &mut ExtState,
43        _memory: &mut Memory,
44        _program_counter: &mut PC,
45        _system_instruction_handler: &mut InstructionHandler,
46    ) -> Result<
47        ControlFlow<(), (Self::Reg, <Self::Reg as Register>::Type)>,
48        ExecutionError<Reg::Type, CustomError>,
49    > {
50        match self {
51            Self::Aes32Dsi {
52                rd,
53                rs1: _,
54                rs2: _,
55                bs,
56            } => {
57                let v1 = rs1_value;
58                let v2 = rs2_value;
59                Ok(ControlFlow::Continue((
60                    rd,
61                    rv32_zknd_helpers::aes32dsi(v1, v2, bs),
62                )))
63            }
64            Self::Aes32Dsmi {
65                rd,
66                rs1: _,
67                rs2: _,
68                bs,
69            } => {
70                let v1 = rs1_value;
71                let v2 = rs2_value;
72                Ok(ControlFlow::Continue((
73                    rd,
74                    rv32_zknd_helpers::aes32dsmi(v1, v2, bs),
75                )))
76            }
77        }
78    }
79}
ab_riscv_interpreter/rv32/zk/zkn/zknd.rs

ab_riscv_interpreter/rv32/zk/zkn/
zknd.rs
