ab_riscv_interpreter/rv32/zk/zkn/
zknd.rs

1//! RV32 Zknd extension
2
3pub mod rv32_zknd_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::prelude::*;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
15    for Rv32ZkndInstruction<Reg>
16where
17    Reg: Register<Type = u32>,
18    Regs: RegisterFile<Reg>,
19{
20    #[inline(always)]
21    fn execute(
22        self,
23        regs: &mut Regs,
24        _ext_state: &mut ExtState,
25        _memory: &mut Memory,
26        _program_counter: &mut PC,
27        _system_instruction_handler: &mut InstructionHandler,
28    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
29        match self {
30            Self::Aes32Dsi { rd, rs1, rs2, bs } => {
31                let v1 = regs.read(rs1);
32                let v2 = regs.read(rs2);
33                regs.write(rd, rv32_zknd_helpers::aes32dsi(v1, v2, bs));
34            }
35            Self::Aes32Dsmi { rd, rs1, rs2, bs } => {
36                let v1 = regs.read(rs1);
37                let v2 = regs.read(rs2);
38                regs.write(rd, rv32_zknd_helpers::aes32dsmi(v1, v2, bs));
39            }
40        }
41
42        Ok(ControlFlow::Continue(()))
43    }
44}
ab_riscv_interpreter/rv32/zk/zkn/zknd.rs

ab_riscv_interpreter/rv32/zk/zkn/
zknd.rs
