ab_riscv_interpreter/rv32/zk/zbkx/
rv32_zbkx_helpers.rs

1//! Opaque helpers for Zbkx extension
2
3use crate::const_utils::ConstRange;
4use const_fn_specialization::const_fn_specialization;
5
6#[const_fn_specialization]
7#[inline]
8#[doc(hidden)]
9#[cfg_attr(feature = "no-panic", no_panic_const::no_panic)]
10pub fn xperm4(rs1: u32, rs2: u32) -> u32 {
11    // TODO: Miri is excluded because corresponding intrinsic is not implemented there
12    cfg_select! {
13        all(not(miri), target_arch = "riscv32", target_feature = "zbkx") => {
14            // SAFETY: Compile-time checked for supported feature
15            unsafe { core::arch::riscv32::xperm4(rs1 as usize, rs2 as usize) as u32 }
16        }
17        _ => {
18            use core::simd::num::SimdUint;
19            use core::simd::{simd_swizzle, u32x8};
20
21            const SHIFT: u32x8 = u32x8::from_array([0, 4, 8, 12, 16, 20, 24, 28]);
22            const MASK: u32x8 = u32x8::splat(0xf);
23
24            // Unpack nibbles of rs1 into bytes via SIMD: broadcast, shift per-lane, mask
25            let lut = (u32x8::splat(rs1) >> SHIFT) & MASK;
26            // Unpack nibbles of rs2 into byte indices via SIMD
27            let idx = (u32x8::splat(rs2) >> SHIFT) & MASK;
28            // For each nibble of rs2, look up from lut (out-of-bounds -> 0 via swizzle_dyn)
29            let nibbles = lut.cast().swizzle_dyn(idx.cast());
30            // Pack nibbles back: interleave even/odd lanes and fold into bytes
31            let lo = simd_swizzle!(nibbles, [0, 2, 4, 6]);
32            let hi = simd_swizzle!(nibbles, [1, 3, 5, 7]);
33            u32::from_le_bytes((lo | (hi << 4)).to_array())
34        }
35    }
36}
37
38#[const_fn_specialization]
39#[inline]
40#[doc(hidden)]
41#[cfg_attr(feature = "no-panic", no_panic_const::no_panic)]
42pub const fn xperm4(rs1: u32, rs2: u32) -> u32 {
43    let mut result = 0;
44
45    // Each nibble of `rs2` selects a nibble of `rs1`, out of bounds selection yields zero
46    for nibble in ConstRange::new(0, u32::BITS / 4) {
47        let index = (rs2 >> (nibble * 4)) & 0xf;
48
49        if index < 8 {
50            result |= ((rs1 >> (index * 4)) & 0xf) << (nibble * 4);
51        }
52    }
53
54    result
55}
56
57#[const_fn_specialization]
58#[inline]
59#[doc(hidden)]
60#[cfg_attr(feature = "no-panic", no_panic_const::no_panic)]
61pub fn xperm8(rs1: u32, rs2: u32) -> u32 {
62    // TODO: Miri is excluded because corresponding intrinsic is not implemented there
63    cfg_select! {
64        all(not(miri), target_arch = "riscv32", target_feature = "zbkx") => {
65            // SAFETY: Compile-time checked for supported feature
66            unsafe { core::arch::riscv32::xperm8(rs1 as usize, rs2 as usize) as u32 }
67        }
68        _ => {
69            use core::simd::u8x4;
70
71            let lut = u8x4::from_array(rs1.to_le_bytes());
72            let idx = u8x4::from_array(rs2.to_le_bytes());
73
74            let result = lut.swizzle_dyn(idx);
75
76            u32::from_le_bytes(result.to_array())
77        }
78    }
79}
80
81#[const_fn_specialization]
82#[inline]
83#[doc(hidden)]
84#[cfg_attr(feature = "no-panic", no_panic_const::no_panic)]
85pub const fn xperm8(rs1: u32, rs2: u32) -> u32 {
86    let mut result = 0;
87
88    // Each byte of `rs2` selects a byte of `rs1`, out of bounds selection yields zero
89    for byte in ConstRange::new(0, u32::BITS / 8) {
90        let index = (rs2 >> (byte * 8)) & 0xff;
91
92        if index < 4 {
93            result |= ((rs1 >> (index * 8)) & 0xff) << (byte * 8);
94        }
95    }
96
97    result
98}
ab_riscv_interpreter/rv32/zk/zbkx/rv32_zbkx_helpers.rs

ab_riscv_interpreter/rv32/zk/zbkx/
rv32_zbkx_helpers.rs
