ab_riscv_interpreter/rv32/
zalasr.rs

1//! RV32 Zalasr extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{
7    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
8    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
10    ThreadedExecutionResult, VirtualMemory,
11};
12use ab_riscv_macros::instruction_execution;
13use ab_riscv_primitives::prelude::*;
14
15#[instruction_execution]
16const impl<Reg> ExecutableInstructionOperands for Rv32ZalasrInstruction<Reg> where
17    Reg: Register<Type = u32>
18{
19}
20
21#[instruction_execution]
22const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZalasrInstruction<Reg> where
23    Reg: Register<Type = u32>
24{
25}
26
27#[instruction_execution]
28const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
29    for Rv32ZalasrInstruction<Reg>
30where
31    Reg: [const] Register<Type = u32>,
32    Regs: [const] RegisterFile<Reg>,
33    Memory: [const] VirtualMemory,
34{
35    #[inline(always)]
36    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
37    fn execute(
38        self,
39        Rs1Rs2OperandValues {
40            rs1_value,
41            rs2_value,
42        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
43        _regs: &mut Regs,
44        _env: &mut Env,
45        memory: &mut Memory,
46        _program_counter: &mut PC,
47    ) -> ExecutionResult<Self::Reg> {
48        match self {
49            Self::LbAq { rd, rs1: _, rl: _ } => {
50                let addr = u64::from(rs1_value);
51                let value = i32::from(memory.read::<i8>(addr)?);
52                ExecutionResult::Continue {
53                    rd,
54                    value: value.cast_unsigned(),
55                }
56            }
57            Self::LhAq { rd, rs1: _, rl: _ } => {
58                let addr = u64::from(rs1_value);
59                let value = i32::from(memory.read::<i16>(addr)?);
60                ExecutionResult::Continue {
61                    rd,
62                    value: value.cast_unsigned(),
63                }
64            }
65            Self::LwAq { rd, rs1: _, rl: _ } => {
66                let addr = u64::from(rs1_value);
67                let value = memory.read::<u32>(addr)?;
68                ExecutionResult::Continue { rd, value }
69            }
70            Self::SbRl {
71                rs1: _,
72                rs2: _,
73                aq: _,
74            } => {
75                let addr = u64::from(rs1_value);
76                memory.write(addr, rs2_value as u8)?;
77                ExecutionResult::ContinueNoWrite
78            }
79            Self::ShRl {
80                rs1: _,
81                rs2: _,
82                aq: _,
83            } => {
84                let addr = u64::from(rs1_value);
85                memory.write(addr, rs2_value as u16)?;
86                ExecutionResult::ContinueNoWrite
87            }
88            Self::SwRl {
89                rs1: _,
90                rs2: _,
91                aq: _,
92            } => {
93                let addr = u64::from(rs1_value);
94                memory.write(addr, rs2_value)?;
95                ExecutionResult::ContinueNoWrite
96            }
97        }
98    }
99}
ab_riscv_interpreter/rv32/zalasr.rs

ab_riscv_interpreter/rv32/
zalasr.rs
