ab_riscv_interpreter/rv32/
zacas.rs

1//! RV32 Zacas extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::rv32::a::amo_helpers;
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
10    PackedAddress, RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
11    ThreadedExecutableInstruction, ThreadedExecutionResult, VirtualMemory,
12};
13use ab_riscv_macros::instruction_execution;
14use ab_riscv_primitives::prelude::*;
15
16#[instruction_execution]
17const impl<Reg, Hart> ExecutableInstructionOperands for Rv32ZacasInstruction<Hart>
18where
19    Reg: Register<Type = u32>,
20    Hart: HartConfig<Reg = Reg>,
21{
22}
23
24#[instruction_execution]
25const impl<Reg, Hart, Env> ExecutableInstructionCsr<Env> for Rv32ZacasInstruction<Hart>
26where
27    Reg: Register<Type = u32>,
28    Hart: HartConfig<Reg = Reg>,
29{
30}
31
32#[instruction_execution]
33const impl<Reg, Hart, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
34    for Rv32ZacasInstruction<Hart>
35where
36    Reg: [const] Register<Type = u32>,
37    Hart: HartConfig<Reg = Reg>,
38    Regs: [const] RegisterFile<Reg>,
39    Memory: [const] VirtualMemory,
40{
41    #[inline(always)]
42    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
43    fn execute(
44        self,
45        Rs1Rs2OperandValues {
46            rs1_value,
47            rs2_value,
48        }: Rs1Rs2OperandValues<Reg::Type>,
49        regs: &mut Regs,
50        _env: &mut Env,
51        memory: &mut Memory,
52        _program_counter: &PC,
53    ) -> ExecutionResult<Reg> {
54        match self {
55            Self::AmocasW {
56                rd,
57                rs1: _,
58                rs2: _,
59                aq: _,
60                rl: _,
61            } => {
62                let addr = u64::from(rs1_value);
63                // The 4-byte access must not cross a misaligned atomicity granule (4096 bytes)
64                // boundary
65                if addr / 4096 != (addr + 3) / 4096 {
66                    ::core::hint::cold_path();
67                    return ExecutionResult::Err(ExecutionError::MisalignedAtomic {
68                        address: PackedAddress::new(addr),
69                    });
70                }
71                let compare = regs.read(rd);
72                let old = amo_helpers::amo_read::<u32, _, _>(memory, addr)?;
73                if old == compare {
74                    memory.write(addr, rs2_value)?;
75                }
76                ExecutionResult::Continue { rd, value: old }
77            }
78            Self::AmocasD {
79                rd,
80                rs1: _,
81                rs2,
82                rd_hi,
83                rs2_hi,
84                aq: _,
85                rl: _,
86            } => {
87                let addr = u64::from(rs1_value);
88                // The 8-byte access must not cross a misaligned atomicity granule (4096 bytes)
89                // boundary
90                if addr / 4096 != (addr + 7) / 4096 {
91                    ::core::hint::cold_path();
92                    return ExecutionResult::Err(ExecutionError::MisalignedAtomic {
93                        address: PackedAddress::new(addr),
94                    });
95                }
96                // Per spec, when the first register of a pair is `x0`, BOTH halves of that pair
97                // read as zero - not just the literal `x0` half. `compare_lo`/`rs2_value` are
98                // already 0 in that case since `x0` is hardwired, but `compare_hi`/`swap_hi`
99                // need an explicit override since `rd_hi`/`rs2_hi` are real registers.
100                let compare_lo = regs.read(rd);
101                let compare_hi = if rd == Reg::ZERO { 0 } else { regs.read(rd_hi) };
102                let swap_hi = if rs2 == Reg::ZERO {
103                    0
104                } else {
105                    regs.read(rs2_hi)
106                };
107                let old_lo = amo_helpers::amo_read::<u32, _, _>(memory, addr)?;
108                let old_hi = amo_helpers::amo_read::<u32, _, _>(memory, addr + 4)?;
109                if old_lo == compare_lo && old_hi == compare_hi {
110                    memory.write(addr, rs2_value)?;
111                    memory.write(addr + 4, swap_hi)?;
112                }
113                // Per spec, when `rd == x0` the whole register-pair write (both halves) is
114                // skipped, not just the low half (which is a no-op anyway since x0 is
115                // hardwired). Only `rd_hi` needs an explicit guard since it's a real register.
116                if rd != Reg::ZERO {
117                    regs.write(rd_hi, old_hi);
118                }
119                ExecutionResult::Continue { rd, value: old_lo }
120            }
121        }
122    }
123}
ab_riscv_interpreter/rv32/zacas.rs

ab_riscv_interpreter/rv32/
zacas.rs
