ab_riscv_interpreter/rv32/
m.rs

1//! RV32 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
8use ab_riscv_macros::instruction_execution;
9use ab_riscv_primitives::prelude::*;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
15    for Rv32MInstruction<Reg>
16where
17    Reg: Register<Type = u32>,
18    Regs: RegisterFile<Reg>,
19{
20    #[inline(always)]
21    fn execute(
22        self,
23        regs: &mut Regs,
24        _ext_state: &mut ExtState,
25        _memory: &mut Memory,
26        _program_counter: &mut PC,
27        _system_instruction_handler: &mut InstructionHandler,
28    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
29        match self {
30            Self::Mul { rd, rs1, rs2 } => {
31                let value = regs.read(rs1).wrapping_mul(regs.read(rs2));
32                regs.write(rd, value);
33            }
34            Self::Mulh { rd, rs1, rs2 } => {
35                // Signed × signed: widen to i64, take upper 32 bits
36                let (_lo, prod) = regs
37                    .read(rs1)
38                    .cast_signed()
39                    .widening_mul(regs.read(rs2).cast_signed());
40                regs.write(rd, prod.cast_unsigned());
41            }
42            Self::Mulhsu { rd, rs1, rs2 } => {
43                // Signed × unsigned: widen to i64, take upper 32 bits
44                let prod = i64::from(regs.read(rs1).cast_signed()) * i64::from(regs.read(rs2));
45                let value = prod >> 32;
46                regs.write(rd, value.cast_unsigned() as u32);
47            }
48            Self::Mulhu { rd, rs1, rs2 } => {
49                // Unsigned × unsigned: widen to u64, take upper 32 bits
50                let prod = u64::from(regs.read(rs1)) * u64::from(regs.read(rs2));
51                let value = prod >> 32;
52                regs.write(rd, value as u32);
53            }
54            Self::Div { rd, rs1, rs2 } => {
55                let dividend = regs.read(rs1).cast_signed();
56                let divisor = regs.read(rs2).cast_signed();
57                let value = if divisor == 0 {
58                    -1i32
59                } else if dividend == i32::MIN && divisor == -1 {
60                    i32::MIN
61                } else {
62                    dividend / divisor
63                };
64                regs.write(rd, value.cast_unsigned());
65            }
66            Self::Divu { rd, rs1, rs2 } => {
67                let dividend = regs.read(rs1);
68                let divisor = regs.read(rs2);
69                let value = dividend.checked_div(divisor).unwrap_or(u32::MAX);
70                regs.write(rd, value);
71            }
72            Self::Rem { rd, rs1, rs2 } => {
73                let dividend = regs.read(rs1).cast_signed();
74                let divisor = regs.read(rs2).cast_signed();
75                let value = if divisor == 0 {
76                    dividend
77                } else if dividend == i32::MIN && divisor == -1 {
78                    0
79                } else {
80                    dividend % divisor
81                };
82                regs.write(rd, value.cast_unsigned());
83            }
84            Self::Remu { rd, rs1, rs2 } => {
85                let dividend = regs.read(rs1);
86                let divisor = regs.read(rs2);
87                let value = if divisor == 0 {
88                    dividend
89                } else {
90                    dividend % divisor
91                };
92                regs.write(rd, value);
93            }
94        }
95
96        Ok(ControlFlow::Continue(()))
97    }
98}
ab_riscv_interpreter/rv32/m.rs

ab_riscv_interpreter/rv32/
m.rs
