ab_riscv_interpreter/rv32/
m.rs

1//! RV32 M extension
2
3#[cfg(test)]
4mod tests;
5pub mod zmmul;
6
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
10    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
11    ThreadedExecutionResult,
12};
13use ab_riscv_macros::instruction_execution;
14use ab_riscv_primitives::prelude::*;
15
16#[instruction_execution]
17const impl<Reg, Hart> ExecutableInstructionOperands for Rv32MInstruction<Hart>
18where
19    Reg: Register<Type = u32>,
20    Hart: HartConfig<Reg = Reg>,
21{
22}
23
24#[instruction_execution]
25const impl<Reg, Hart, Env> ExecutableInstructionCsr<Env> for Rv32MInstruction<Hart>
26where
27    Reg: Register<Type = u32>,
28    Hart: HartConfig<Reg = Reg>,
29{
30}
31
32#[instruction_execution]
33const impl<Reg, Hart, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
34    for Rv32MInstruction<Hart>
35where
36    Reg: [const] Register<Type = u32>,
37    Hart: HartConfig<Reg = Reg>,
38    Regs: [const] RegisterFile<Reg>,
39{
40    #[inline(always)]
41    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
42    fn execute(
43        self,
44        Rs1Rs2OperandValues {
45            rs1_value,
46            rs2_value,
47        }: Rs1Rs2OperandValues<Reg::Type>,
48        _regs: &mut Regs,
49        _env: &mut Env,
50        _memory: &mut Memory,
51        _program_counter: &PC,
52    ) -> ExecutionResult<Reg> {
53        match self {
54            Self::Div { rd, rs1: _, rs2: _ } => {
55                let dividend = rs1_value.cast_signed();
56                let divisor = rs2_value.cast_signed();
57                let value = if divisor == 0 {
58                    -1i32
59                } else if dividend == i32::MIN && divisor == -1 {
60                    i32::MIN
61                } else {
62                    dividend / divisor
63                };
64                ExecutionResult::Continue {
65                    rd,
66                    value: value.cast_unsigned(),
67                }
68            }
69            Self::Divu { rd, rs1: _, rs2: _ } => {
70                let dividend = rs1_value;
71                let divisor = rs2_value;
72                let value = dividend.checked_div(divisor).unwrap_or(u32::MAX);
73                ExecutionResult::Continue { rd, value }
74            }
75            Self::Rem { rd, rs1: _, rs2: _ } => {
76                let dividend = rs1_value.cast_signed();
77                let divisor = rs2_value.cast_signed();
78                #[expect(
79                    clippy::modulo_arithmetic,
80                    reason = "This is what the code is supposed to do"
81                )]
82                let value = if divisor == 0 {
83                    dividend
84                } else if dividend == i32::MIN && divisor == -1 {
85                    0
86                } else {
87                    dividend % divisor
88                };
89                ExecutionResult::Continue {
90                    rd,
91                    value: value.cast_unsigned(),
92                }
93            }
94            Self::Remu { rd, rs1: _, rs2: _ } => {
95                let dividend = rs1_value;
96                let divisor = rs2_value;
97                let value = if divisor == 0 {
98                    dividend
99                } else {
100                    dividend % divisor
101                };
102                ExecutionResult::Continue { rd, value }
103            }
104        }
105    }
106}
ab_riscv_interpreter/rv32/m.rs

ab_riscv_interpreter/rv32/
m.rs
