ab_riscv_interpreter/rv32/b/
zbs.rs

1//! RV32 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
7use ab_riscv_macros::instruction_execution;
8use ab_riscv_primitives::prelude::*;
9use core::ops::ControlFlow;
10
11#[instruction_execution]
12impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
13    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    for Rv32ZbsInstruction<Reg>
15where
16    Reg: Register<Type = u32>,
17    Regs: RegisterFile<Reg>,
18{
19    #[inline(always)]
20    fn execute(
21        self,
22        regs: &mut Regs,
23        _ext_state: &mut ExtState,
24        _memory: &mut Memory,
25        _program_counter: &mut PC,
26        _system_instruction_handler: &mut InstructionHandler,
27    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
28        match self {
29            Self::Bset { rd, rs1, rs2 } => {
30                // Only the bottom 5 bits for RV32
31                let index = regs.read(rs2) & 0x1f;
32                let result = regs.read(rs1) | (1u32 << index);
33                regs.write(rd, result);
34            }
35            Self::Bseti { rd, rs1, shamt } => {
36                let index = shamt;
37                let result = regs.read(rs1) | (1u32 << index);
38                regs.write(rd, result);
39            }
40            Self::Bclr { rd, rs1, rs2 } => {
41                let index = regs.read(rs2) & 0x1f;
42                let result = regs.read(rs1) & !(1u32 << index);
43                regs.write(rd, result);
44            }
45            Self::Bclri { rd, rs1, shamt } => {
46                let index = shamt;
47                let result = regs.read(rs1) & !(1u32 << index);
48                regs.write(rd, result);
49            }
50            Self::Binv { rd, rs1, rs2 } => {
51                let index = regs.read(rs2) & 0x1f;
52                let result = regs.read(rs1) ^ (1u32 << index);
53                regs.write(rd, result);
54            }
55            Self::Binvi { rd, rs1, shamt } => {
56                let index = shamt;
57                let result = regs.read(rs1) ^ (1u32 << index);
58                regs.write(rd, result);
59            }
60            Self::Bext { rd, rs1, rs2 } => {
61                let index = regs.read(rs2) & 0x1f;
62                let result = (regs.read(rs1) >> index) & 1;
63                regs.write(rd, result);
64            }
65            Self::Bexti { rd, rs1, shamt } => {
66                let index = shamt;
67                let result = (regs.read(rs1) >> index) & 1;
68                regs.write(rd, result);
69            }
70        }
71
72        Ok(ControlFlow::Continue(()))
73    }
74}
ab_riscv_interpreter/rv32/b/zbs.rs

ab_riscv_interpreter/rv32/b/
zbs.rs
