ab_riscv_interpreter/rv32/b/
zbs.rs

1//! RV32 Zbs extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{
7    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
8    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
10    ThreadedExecutionResult,
11};
12use ab_riscv_macros::instruction_execution;
13use ab_riscv_primitives::prelude::*;
14
15#[instruction_execution]
16const impl<Reg> ExecutableInstructionOperands for Rv32ZbsInstruction<Reg> where
17    Reg: Register<Type = u32>
18{
19}
20
21#[instruction_execution]
22const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbsInstruction<Reg> where
23    Reg: Register<Type = u32>
24{
25}
26
27#[instruction_execution]
28const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
29    for Rv32ZbsInstruction<Reg>
30where
31    Reg: [const] Register<Type = u32>,
32    Regs: [const] RegisterFile<Reg>,
33{
34    #[inline(always)]
35    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
36    fn execute(
37        self,
38        Rs1Rs2OperandValues {
39            rs1_value,
40            rs2_value,
41        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
42        _regs: &mut Regs,
43        _env: &mut Env,
44        _memory: &mut Memory,
45        _program_counter: &mut PC,
46    ) -> ExecutionResult<Self::Reg> {
47        match self {
48            Self::Bset { rd, rs1: _, rs2: _ } => {
49                // Only the bottom 5 bits for RV32
50                let index = rs2_value & 0x1f;
51                let result = rs1_value | (1u32 << index);
52                ExecutionResult::Continue { rd, value: result }
53            }
54            Self::Bseti { rd, rs1: _, shamt } => {
55                let index = shamt;
56                let result = rs1_value | (1u32 << index);
57                ExecutionResult::Continue { rd, value: result }
58            }
59            Self::Bclr { rd, rs1: _, rs2: _ } => {
60                let index = rs2_value & 0x1f;
61                let result = rs1_value & !(1u32 << index);
62                ExecutionResult::Continue { rd, value: result }
63            }
64            Self::Bclri { rd, rs1: _, shamt } => {
65                let index = shamt;
66                let result = rs1_value & !(1u32 << index);
67                ExecutionResult::Continue { rd, value: result }
68            }
69            Self::Binv { rd, rs1: _, rs2: _ } => {
70                let index = rs2_value & 0x1f;
71                let result = rs1_value ^ (1u32 << index);
72                ExecutionResult::Continue { rd, value: result }
73            }
74            Self::Binvi { rd, rs1: _, shamt } => {
75                let index = shamt;
76                let result = rs1_value ^ (1u32 << index);
77                ExecutionResult::Continue { rd, value: result }
78            }
79            Self::Bext { rd, rs1: _, rs2: _ } => {
80                let index = rs2_value & 0x1f;
81                let result = (rs1_value >> index) & 1;
82                ExecutionResult::Continue { rd, value: result }
83            }
84            Self::Bexti { rd, rs1: _, shamt } => {
85                let index = shamt;
86                let result = (rs1_value >> index) & 1;
87                ExecutionResult::Continue { rd, value: result }
88            }
89        }
90    }
91}
ab_riscv_interpreter/rv32/b/zbs.rs

ab_riscv_interpreter/rv32/b/
zbs.rs
