ab_riscv_interpreter/rv32/b/
zbc.rs1pub mod rv32_zbc_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{
8 ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9 ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
10 RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
11 ThreadedExecutionResult,
12};
13use ab_riscv_macros::instruction_execution;
14use ab_riscv_primitives::prelude::*;
15
16#[instruction_execution]
17const impl<Reg> ExecutableInstructionOperands for Rv32ZbcInstruction<Reg> where
18 Reg: Register<Type = u32>
19{
20}
21
22#[instruction_execution]
23const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbcInstruction<Reg> where
24 Reg: Register<Type = u32>
25{
26}
27
28#[instruction_execution]
29const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
30 for Rv32ZbcInstruction<Reg>
31where
32 Reg: [const] Register<Type = u32>,
33 Regs: [const] RegisterFile<Reg>,
34{
35 #[inline(always)]
36 #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
37 fn execute(
38 self,
39 Rs1Rs2OperandValues {
40 rs1_value,
41 rs2_value,
42 }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
43 _regs: &mut Regs,
44 _env: &mut Env,
45 _memory: &mut Memory,
46 _program_counter: &mut PC,
47 ) -> ExecutionResult<Self::Reg> {
48 match self {
49 Self::Clmul { rd, rs1: _, rs2: _ } => {
50 let a = rs1_value;
51 let b = rs2_value;
52
53 ExecutionResult::Continue {
54 rd,
55 value: rv32_zbc_helpers::clmul(a, b),
56 }
57 }
58 Self::Clmulh { rd, rs1: _, rs2: _ } => {
59 let a = rs1_value;
60 let b = rs2_value;
61
62 ExecutionResult::Continue {
63 rd,
64 value: rv32_zbc_helpers::clmulh(a, b),
65 }
66 }
67 Self::Clmulr { rd, rs1: _, rs2: _ } => {
68 let a = rs1_value;
69 let b = rs2_value;
70
71 ExecutionResult::Continue {
72 rd,
73 value: rv32_zbc_helpers::clmulr(a, b),
74 }
75 }
76 }
77 }
78}