ab_riscv_interpreter/rv32/b/
zbb.rs

1//! RV32 Zbb extension
2
3pub mod rv32_zbb_helpers;
4#[cfg(test)]
5mod tests;
6
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
10};
11use ab_riscv_macros::instruction_execution;
12use ab_riscv_primitives::prelude::*;
13use core::ops::ControlFlow;
14
15#[instruction_execution]
16impl<Reg> ExecutableInstructionOperands for Rv32ZbbInstruction<Reg> where Reg: Register<Type = u32> {}
17
18#[instruction_execution]
19impl<Reg, ExtState, CustomError> ExecutableInstructionCsr<ExtState, CustomError>
20    for Rv32ZbbInstruction<Reg>
21where
22    Reg: Register<Type = u32>,
23{
24}
25
26#[instruction_execution]
27impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
28    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
29    for Rv32ZbbInstruction<Reg>
30where
31    Reg: Register<Type = u32>,
32    Regs: RegisterFile<Reg>,
33{
34    #[inline(always)]
35    fn execute(
36        self,
37        Rs1Rs2OperandValues {
38            rs1_value,
39            rs2_value,
40        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
41        _regs: &mut Regs,
42        _ext_state: &mut ExtState,
43        _memory: &mut Memory,
44        _program_counter: &mut PC,
45        _system_instruction_handler: &mut InstructionHandler,
46    ) -> Result<
47        ControlFlow<(), (Self::Reg, <Self::Reg as Register>::Type)>,
48        ExecutionError<Reg::Type, CustomError>,
49    > {
50        match self {
51            Self::Andn { rd, rs1: _, rs2: _ } => {
52                let value = rs1_value & !rs2_value;
53                Ok(ControlFlow::Continue((rd, value)))
54            }
55            Self::Orn { rd, rs1: _, rs2: _ } => {
56                let value = rs1_value | !rs2_value;
57                Ok(ControlFlow::Continue((rd, value)))
58            }
59            Self::Xnor { rd, rs1: _, rs2: _ } => {
60                let value = !(rs1_value ^ rs2_value);
61                Ok(ControlFlow::Continue((rd, value)))
62            }
63            Self::Clz { rd, rs1: _ } => {
64                let value = rs1_value.leading_zeros();
65                Ok(ControlFlow::Continue((rd, value)))
66            }
67            Self::Ctz { rd, rs1: _ } => {
68                let value = rs1_value.trailing_zeros();
69                Ok(ControlFlow::Continue((rd, value)))
70            }
71            Self::Cpop { rd, rs1: _ } => {
72                let value = rs1_value.count_ones();
73                Ok(ControlFlow::Continue((rd, value)))
74            }
75            Self::Max { rd, rs1: _, rs2: _ } => {
76                let a = rs1_value.cast_signed();
77                let b = rs2_value.cast_signed();
78                let value = a.max(b).cast_unsigned();
79                Ok(ControlFlow::Continue((rd, value)))
80            }
81            Self::Maxu { rd, rs1: _, rs2: _ } => {
82                let value = rs1_value.max(rs2_value);
83                Ok(ControlFlow::Continue((rd, value)))
84            }
85            Self::Min { rd, rs1: _, rs2: _ } => {
86                let a = rs1_value.cast_signed();
87                let b = rs2_value.cast_signed();
88                let value = a.min(b).cast_unsigned();
89                Ok(ControlFlow::Continue((rd, value)))
90            }
91            Self::Minu { rd, rs1: _, rs2: _ } => {
92                let value = rs1_value.min(rs2_value);
93                Ok(ControlFlow::Continue((rd, value)))
94            }
95            Self::Sextb { rd, rs1: _ } => {
96                let value = i32::from(rs1_value as i8).cast_unsigned();
97                Ok(ControlFlow::Continue((rd, value)))
98            }
99            Self::Sexth { rd, rs1: _ } => {
100                let value = i32::from(rs1_value as i16).cast_unsigned();
101                Ok(ControlFlow::Continue((rd, value)))
102            }
103            Self::Zexth { rd, rs1: _ } => {
104                let value = u32::from(rs1_value as u16);
105                Ok(ControlFlow::Continue((rd, value)))
106            }
107            Self::Rol { rd, rs1: _, rs2: _ } => {
108                let shamt = rs2_value & 0x1f;
109                let value = rs1_value.rotate_left(shamt);
110                Ok(ControlFlow::Continue((rd, value)))
111            }
112            Self::Ror { rd, rs1: _, rs2: _ } => {
113                let shamt = rs2_value & 0x1f;
114                let value = rs1_value.rotate_right(shamt);
115                Ok(ControlFlow::Continue((rd, value)))
116            }
117            Self::Rori { rd, rs1: _, shamt } => {
118                let value = rs1_value.rotate_right(u32::from(shamt & 0x1f));
119                Ok(ControlFlow::Continue((rd, value)))
120            }
121            Self::Orcb { rd, rs1: _ } => {
122                let src = rs1_value;
123
124                Ok(ControlFlow::Continue((rd, rv32_zbb_helpers::orc_b(src))))
125            }
126            Self::Rev8 { rd, rs1: _ } => {
127                let value = rs1_value.swap_bytes();
128                Ok(ControlFlow::Continue((rd, value)))
129            }
130        }
131    }
132}
ab_riscv_interpreter/rv32/b/zbb.rs

ab_riscv_interpreter/rv32/b/
zbb.rs
