ab_riscv_interpreter/rv32/b/
zbb.rs

1//! RV32 Zbb extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{ExecutableInstruction, ExecutionError, InterpreterState};
7use ab_riscv_macros::instruction_execution;
8use ab_riscv_primitives::instructions::rv32::b::zbb::Rv32ZbbInstruction;
9use ab_riscv_primitives::registers::general_purpose::Register;
10use core::ops::ControlFlow;
11
12#[instruction_execution]
13impl<Reg, ExtState, Memory, PC, InstructionHandler, CustomError>
14    ExecutableInstruction<
15        InterpreterState<Reg, ExtState, Memory, PC, InstructionHandler, CustomError>,
16        CustomError,
17    > for Rv32ZbbInstruction<Reg>
18where
19    Reg: Register<Type = u32>,
20    [(); Reg::N]:,
21{
22    #[inline(always)]
23    fn execute(
24        self,
25        state: &mut InterpreterState<Reg, ExtState, Memory, PC, InstructionHandler, CustomError>,
26    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
27        match self {
28            Self::Andn { rd, rs1, rs2 } => {
29                let value = state.regs.read(rs1) & !state.regs.read(rs2);
30                state.regs.write(rd, value);
31            }
32            Self::Orn { rd, rs1, rs2 } => {
33                let value = state.regs.read(rs1) | !state.regs.read(rs2);
34                state.regs.write(rd, value);
35            }
36            Self::Xnor { rd, rs1, rs2 } => {
37                let value = !(state.regs.read(rs1) ^ state.regs.read(rs2));
38                state.regs.write(rd, value);
39            }
40            Self::Clz { rd, rs1 } => {
41                let value = state.regs.read(rs1).leading_zeros();
42                state.regs.write(rd, value);
43            }
44            Self::Ctz { rd, rs1 } => {
45                let value = state.regs.read(rs1).trailing_zeros();
46                state.regs.write(rd, value);
47            }
48            Self::Cpop { rd, rs1 } => {
49                let value = state.regs.read(rs1).count_ones();
50                state.regs.write(rd, value);
51            }
52            Self::Max { rd, rs1, rs2 } => {
53                let a = state.regs.read(rs1).cast_signed();
54                let b = state.regs.read(rs2).cast_signed();
55                let value = a.max(b).cast_unsigned();
56                state.regs.write(rd, value);
57            }
58            Self::Maxu { rd, rs1, rs2 } => {
59                let value = state.regs.read(rs1).max(state.regs.read(rs2));
60                state.regs.write(rd, value);
61            }
62            Self::Min { rd, rs1, rs2 } => {
63                let a = state.regs.read(rs1).cast_signed();
64                let b = state.regs.read(rs2).cast_signed();
65                let value = a.min(b).cast_unsigned();
66                state.regs.write(rd, value);
67            }
68            Self::Minu { rd, rs1, rs2 } => {
69                let value = state.regs.read(rs1).min(state.regs.read(rs2));
70                state.regs.write(rd, value);
71            }
72            Self::Sextb { rd, rs1 } => {
73                let value = i32::from(state.regs.read(rs1) as i8).cast_unsigned();
74                state.regs.write(rd, value);
75            }
76            Self::Sexth { rd, rs1 } => {
77                let value = i32::from(state.regs.read(rs1) as i16).cast_unsigned();
78                state.regs.write(rd, value);
79            }
80            Self::Zexth { rd, rs1 } => {
81                let value = u32::from(state.regs.read(rs1) as u16);
82                state.regs.write(rd, value);
83            }
84            Self::Rol { rd, rs1, rs2 } => {
85                let shamt = state.regs.read(rs2) & 0x1f;
86                let value = state.regs.read(rs1).rotate_left(shamt);
87                state.regs.write(rd, value);
88            }
89            Self::Ror { rd, rs1, rs2 } => {
90                let shamt = state.regs.read(rs2) & 0x1f;
91                let value = state.regs.read(rs1).rotate_right(shamt);
92                state.regs.write(rd, value);
93            }
94            Self::Rori { rd, rs1, shamt } => {
95                let value = state.regs.read(rs1).rotate_right(u32::from(shamt & 0x1f));
96                state.regs.write(rd, value);
97            }
98            Self::Orcb { rd, rs1 } => {
99                let src = state.regs.read(rs1);
100                let mut result = 0u32;
101                for i in 0..4 {
102                    let byte = (src >> (i * 8)) & 0xFF;
103                    if byte != 0 {
104                        result |= 0xFF << (i * 8);
105                    }
106                }
107                state.regs.write(rd, result);
108            }
109            Self::Rev8 { rd, rs1 } => {
110                let value = state.regs.read(rs1).swap_bytes();
111                state.regs.write(rd, value);
112            }
113        }
114
115        Ok(ControlFlow::Continue(()))
116    }
117}
ab_riscv_interpreter/rv32/b/zbb.rs

ab_riscv_interpreter/rv32/b/
zbb.rs
