ab_riscv_interpreter/rv32/b/
zba.rs

1//! RV32 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{
7    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
8    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
9    RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, ThreadedExecutableInstruction,
10    ThreadedExecutionResult,
11};
12use ab_riscv_macros::instruction_execution;
13use ab_riscv_primitives::prelude::*;
14
15#[instruction_execution]
16const impl<Reg> ExecutableInstructionOperands for Rv32ZbaInstruction<Reg> where
17    Reg: Register<Type = u32>
18{
19}
20
21#[instruction_execution]
22const impl<Reg, Env> ExecutableInstructionCsr<Env> for Rv32ZbaInstruction<Reg> where
23    Reg: Register<Type = u32>
24{
25}
26
27#[instruction_execution]
28const impl<Reg, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
29    for Rv32ZbaInstruction<Reg>
30where
31    Reg: [const] Register<Type = u32>,
32    Regs: [const] RegisterFile<Reg>,
33{
34    #[inline(always)]
35    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
36    fn execute(
37        self,
38        Rs1Rs2OperandValues {
39            rs1_value,
40            rs2_value,
41        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
42        _regs: &mut Regs,
43        _env: &mut Env,
44        _memory: &mut Memory,
45        _program_counter: &mut PC,
46    ) -> ExecutionResult<Self::Reg> {
47        match self {
48            Self::Sh1add { rd, rs1: _, rs2: _ } => {
49                let value = (rs1_value << 1).wrapping_add(rs2_value);
50                ExecutionResult::Continue { rd, value }
51            }
52            Self::Sh2add { rd, rs1: _, rs2: _ } => {
53                let value = (rs1_value << 2).wrapping_add(rs2_value);
54                ExecutionResult::Continue { rd, value }
55            }
56            Self::Sh3add { rd, rs1: _, rs2: _ } => {
57                let value = (rs1_value << 3).wrapping_add(rs2_value);
58                ExecutionResult::Continue { rd, value }
59            }
60        }
61    }
62}
ab_riscv_interpreter/rv32/b/zba.rs

ab_riscv_interpreter/rv32/b/
zba.rs
