ab_riscv_interpreter/rv32/b/
zba.rs

1//! RV32 Zba extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::{ExecutableInstruction, ExecutionError, RegisterFile};
7use ab_riscv_macros::instruction_execution;
8use ab_riscv_primitives::prelude::*;
9use core::ops::ControlFlow;
10
11#[instruction_execution]
12impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
13    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
14    for Rv32ZbaInstruction<Reg>
15where
16    Reg: Register<Type = u32>,
17    Regs: RegisterFile<Reg>,
18{
19    #[inline(always)]
20    fn execute(
21        self,
22        regs: &mut Regs,
23        _ext_state: &mut ExtState,
24        _memory: &mut Memory,
25        _program_counter: &mut PC,
26        _system_instruction_handler: &mut InstructionHandler,
27    ) -> Result<ControlFlow<()>, ExecutionError<Reg::Type, CustomError>> {
28        match self {
29            Self::Sh1add { rd, rs1, rs2 } => {
30                let value = (regs.read(rs1) << 1).wrapping_add(regs.read(rs2));
31                regs.write(rd, value);
32            }
33            Self::Sh2add { rd, rs1, rs2 } => {
34                let value = (regs.read(rs1) << 2).wrapping_add(regs.read(rs2));
35                regs.write(rd, value);
36            }
37            Self::Sh3add { rd, rs1, rs2 } => {
38                let value = (regs.read(rs1) << 3).wrapping_add(regs.read(rs2));
39                regs.write(rd, value);
40            }
41        }
42
43        Ok(ControlFlow::Continue(()))
44    }
45}
ab_riscv_interpreter/rv32/b/zba.rs

ab_riscv_interpreter/rv32/b/
zba.rs
