ab_riscv_interpreter/rv32/a/
zalrsc.rs

1//! RV32 Zalrsc extension
2
3#[cfg(test)]
4mod tests;
5
6use crate::rv32::a::{ReservationSet, amo_helpers};
7use crate::{
8    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands, ExecutionError,
9    ExecutionResult, FetchInstructionResult, InstructionFetcher, OpaqueThreadedExecutionResult,
10    PackedAddress, RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands,
11    ThreadedExecutableInstruction, ThreadedExecutionResult, VirtualMemory,
12};
13use ab_riscv_macros::instruction_execution;
14use ab_riscv_primitives::prelude::*;
15
16#[instruction_execution]
17const impl<Reg, Hart> ExecutableInstructionOperands for Rv32ZalrscInstruction<Hart>
18where
19    Reg: Register<Type = u32>,
20    Hart: HartConfig<Reg = Reg>,
21{
22}
23
24#[instruction_execution]
25const impl<Reg, Hart, Env> ExecutableInstructionCsr<Env> for Rv32ZalrscInstruction<Hart>
26where
27    Reg: Register<Type = u32>,
28    Hart: HartConfig<Reg = Reg>,
29{
30}
31
32#[instruction_execution]
33const impl<Reg, Hart, Regs, Env, Memory, PC> ExecutableInstruction<Regs, Env, Memory, PC>
34    for Rv32ZalrscInstruction<Hart>
35where
36    Reg: [const] Register<Type = u32>,
37    Hart: HartConfig<Reg = Reg>,
38    Regs: [const] RegisterFile<Reg>,
39    Memory: [const] VirtualMemory,
40    Env: [const] ReservationSet<Reg>,
41{
42    #[inline(always)]
43    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
44    fn execute(
45        self,
46        Rs1Rs2OperandValues {
47            rs1_value,
48            rs2_value,
49        }: Rs1Rs2OperandValues<Reg::Type>,
50        _regs: &mut Regs,
51        env: &mut Env,
52        memory: &mut Memory,
53        _program_counter: &PC,
54    ) -> ExecutionResult<Reg> {
55        match self {
56            Self::Lr {
57                rd,
58                rs1: _,
59                aq: _,
60                rl: _,
61            } => {
62                if !rs1_value.is_multiple_of(4) {
63                    ::core::hint::cold_path();
64                    return ExecutionResult::Err(ExecutionError::MisalignedRead {
65                        address: PackedAddress::new(u64::from(rs1_value)),
66                    });
67                }
68                let value = memory.read::<u32>(u64::from(rs1_value))?;
69                env.set_reservation(rs1_value);
70                ExecutionResult::Continue { rd, value }
71            }
72            Self::Sc {
73                rd,
74                rs1: _,
75                rs2: _,
76                aq: _,
77                rl: _,
78            } => {
79                if !rs1_value.is_multiple_of(4) {
80                    ::core::hint::cold_path();
81                    return ExecutionResult::Err(ExecutionError::MisalignedWrite {
82                        address: PackedAddress::new(u64::from(rs1_value)),
83                    });
84                }
85                let success = env.reservation() == Some(rs1_value);
86                env.clear_reservation();
87
88                if success {
89                    memory.write(u64::from(rs1_value), rs2_value)?;
90                    ExecutionResult::Continue { rd, value: 0 }
91                } else {
92                    // A failing `sc` (lost/no reservation) still checks its target address for a
93                    // Store/AMO access fault, exactly as a successful one would - only the actual
94                    // write is skipped. `amo_read` (not a plain `memory.read`) both probes the
95                    // same address range a write would use, side-effect-free, and classifies any
96                    // fault as Store/AMO rather than Load, matching a real `sc`'s own fault cause.
97                    amo_helpers::amo_read::<u32, _, _>(memory, u64::from(rs1_value))?;
98                    ExecutionResult::Continue { rd, value: 1 }
99                }
100            }
101        }
102    }
103}
ab_riscv_interpreter/rv32/a/zalrsc.rs

ab_riscv_interpreter/rv32/a/
zalrsc.rs
