ab_riscv_interpreter/rv32/
a.rs

1//! RV32 A extension
2
3pub mod zaamo;
4pub mod zalrsc;
5
6use crate::{
7    ExecutableInstruction, ExecutableInstructionCsr, ExecutableInstructionOperands,
8    ExecutableInstructionResult, RegisterFile, Rs1Rs2OperandValues, Rs1Rs2Operands, VirtualMemory,
9};
10use ab_riscv_macros::instruction_execution;
11use ab_riscv_primitives::prelude::*;
12use core::ops::ControlFlow;
13
14/// Reservation set used to implement `Zalrsc` extension's `lr`/`sc` instruction pairs.
15///
16/// `lr` places a reservation on an address, and a subsequent `sc` succeeds only if the reservation
17/// is still held for the same address. Regardless of success or failure, executing `sc` always
18/// invalidates the reservation, as does a subsequent `lr`.
19pub const trait ReservationSet<Reg>
20where
21    Reg: [const] Register,
22{
23    /// Returns the address of the currently held reservation, if any
24    fn reservation(&self) -> Option<Reg::Type>;
25
26    /// Place a reservation on `address`, replacing any previously held reservation
27    fn set_reservation(&mut self, address: Reg::Type);
28
29    /// Clear any currently held reservation
30    fn clear_reservation(&mut self);
31}
32
33#[instruction_execution]
34const impl<Reg> ExecutableInstructionOperands for Rv32AInstruction<Reg> where
35    Reg: Register<Type = u32>
36{
37}
38
39#[instruction_execution]
40const impl<Reg, ExtState, CustomError> ExecutableInstructionCsr<ExtState, CustomError>
41    for Rv32AInstruction<Reg>
42where
43    Reg: Register<Type = u32>,
44{
45}
46
47#[instruction_execution]
48const impl<Reg, Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
49    ExecutableInstruction<Regs, ExtState, Memory, PC, InstructionHandler, CustomError>
50    for Rv32AInstruction<Reg>
51where
52    Reg: [const] Register<Type = u32>,
53    Regs: [const] RegisterFile<Reg>,
54    Memory: [const] VirtualMemory,
55    ExtState: [const] ReservationSet<Reg>,
56{
57    #[inline(always)]
58    #[cfg_attr(feature = "no-panic", no_panic_const::no_panic(const))]
59    fn execute(
60        self,
61        Rs1Rs2OperandValues {
62            rs1_value,
63            rs2_value,
64        }: Rs1Rs2OperandValues<<Self::Reg as Register>::Type>,
65        _regs: &mut Regs,
66        ext_state: &mut ExtState,
67        memory: &mut Memory,
68        _program_counter: &mut PC,
69        _system_instruction_handler: &mut InstructionHandler,
70    ) -> ExecutableInstructionResult<(), Self, CustomError> {
71        Ok(ControlFlow::Continue(Default::default()))
72    }
73}
ab_riscv_interpreter/rv32/a.rs

ab_riscv_interpreter/rv32/
a.rs
