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sign_extend_to_reg

ab_riscv_interpreter::v::zve64x::perm::zve64x_perm_helpers

Function sign_extend_to_reg 

Source 
pub fn sign_extend_to_reg<Reg>(val: u64, sew: Vsew) -> Reg::Type
where
    Reg: Register,
Expand description

Sign-extend the low sew.bits() of val to the register type width.

The arithmetic is performed entirely in 64-bit signed integer space: we shift the SEW-wide value left to place its sign bit at bit 63, then arithmetic-right-shift back to propagate it. The resulting u64 is then narrowed to Reg::Type (32 or 64 bits) by combining via From<u32> - the only integer conversion in the Register::Type trait bounds.

For RV32 (Reg::XLEN == 32) the low 32 bits are already the correct sign-extended result because the arithmetic shift propagates the sign across all 64 bits and then we discard the upper half.

For RV64 (Reg::XLEN == 64) we must preserve all 64 bits. Since Reg::Type: From<u32> and Reg::Type: Shl<u8>, we reconstruct the 64-bit value by OR-ing two 32-bit halves shifted into position.